MANUFACTURING METHOD OF CRYSTALLINE SOLID LAYER

    公开(公告)号:JP2002118107A

    公开(公告)日:2002-04-19

    申请号:JP2001251144

    申请日:2001-08-22

    Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a sufficiently uniform layer regarding layer thickness, stoichiometry, and electrical characteristics, and for manufacturing a ferroelectric or paraelectric solid layer by vapor deposition. SOLUTION: In the method for manufacturing the crystalline solid layer on a substrate by the vapor deposition, at least one assistant other than a departure gas containing the element of the solid layer that can be deposited is introduced into a reaction chamber. In this case, the assistant has a dipole moment, and contains a molecule adhering onto the surface of the substrate having the dipole moment in a vertical direction to the surface of the substrate quickly during a deposition process, thus determining the crystal structure of the solid layer in advance.

    SEMICONDUCTOR MEMORY WITH MEMORY CELLS COMPRISING A VERTICAL SELECTION TRANSISTOR AND METHOD FOR PRODUCTION THEREOF
    2.
    发明申请
    SEMICONDUCTOR MEMORY WITH MEMORY CELLS COMPRISING A VERTICAL SELECTION TRANSISTOR AND METHOD FOR PRODUCTION THEREOF 审中-公开
    包含垂直选择晶体管的具有存储器单元的半导体存储器及其制造方法

    公开(公告)号:WO03028104A3

    公开(公告)日:2003-08-14

    申请号:PCT/DE0202980

    申请日:2002-08-14

    Abstract: A trench capacitor (30) is arranged in a first trench (25) for production of a semiconductor memory (5). A first longitudinal trench (55) is arranged in the substrate (15) next to the first trench (25) and parallel thereto on the other side of the first trench (25), a second longitudinal trench (60) is arranged therein. A first spacer word line (70) is arranged in the first longitudinal trench (55) and a second spacer word line (75) is arranged in the second longitudinal trench (60). Connecting webs (80) are arranged in the first trench (25) between the first spacer word line (70) and the second spacer word line (75) with a thickness (110), which is smaller in the direction of the first spacer word line (70) than half the width of the first trench (25) in the direction of the first spacer word line (70).

    Abstract translation: 为了制造半导体存储器(5),沟槽电容器(30)被布置在第一沟槽(25)中。 除了所述第一沟槽(25),第一纵向沟槽(55)和上第一沟槽并行(25),在所述基板的第二纵向沟槽(60)的另一侧(15)被布置。 在第一纵向沟槽(55)中设置第一间隔字线(70),在第二纵向沟槽(60)中设置第二间隔字线(75)。 在所述第一沟槽(25)的连接板(80)设置在所述第一间隔物的字线(70)和具有厚度(110)所述第二间隔的字线(75)(在第一间隔的字线70的方向之间 )小于第一沟槽(25)朝向第一间隔字线(70)的宽度的一半。

    5.
    发明专利
    未知

    公开(公告)号:DE10249207A1

    公开(公告)日:2004-05-13

    申请号:DE10249207

    申请日:2002-10-22

    Abstract: An annular microstructure element, in particular an annularly arranged monolayer or multilayer thin film, is formed over a substrate (S), e.g., for use in a magnetoresistive memory. To that end, a masking layer is applied over the substrate. An opening (C) is etched into the masking layer, so that a partial region of the surface is uncovered. The etching operation is performed in such a way that the opening (C) is formed with an overhang (B). The overhang at least partially shades the uncovered surface from an incident particle beam (TS). A particle beam (TS) is directed at the substrate (S) at an oblique angle (alpha) of incidence. In this case, the substrate (S) is rotated relative to the directed particle beam (TS). From the particle beam, material is thereby deposited annularly on the uncovered surface for the purpose of forming a hole-like microstructure element (R).

    9.
    发明专利
    未知

    公开(公告)号:DE10131709B4

    公开(公告)日:2006-10-26

    申请号:DE10131709

    申请日:2001-06-29

    Abstract: Buried straps are produced on one side in deep trench structures. A PVD process is used to deposit masking material in the recess inclined at an angle. As a result, a masking wedge is produced on the buried strap, on one side in the base region of the recess. The masking wedge serves as a mask during a subsequent anisotropic etching step, which is carried out selectively with respect to the masking wedge, for removing the buried strap on one side.

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