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    12.
    发明专利
    未知

    公开(公告)号：DE10112276C2

    公开(公告)日：2003-02-06

    申请号：DE10112276

    申请日：2001-03-14

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KROENKE MATTHIAS ,  KASKO IGOR ,  WEINRICH VOLKER

    IPC: H01L21/02 ,  H01L21/285 ,  H01L27/115 ,  H01L27/11502 ,  H01L21/8239 ,  H01L27/105

    Abstract: The integrated ferroelectric semiconductor memory is fabricated according to the stack cell principle. A ferroelectric capacitor module is formed on an intermediate oxide above a selection transistor located in or on a semiconductor wafer. The capacitor module is brought into conductive contact by its bottom capacitor electrode with an electrode of the selection transistor by means of an electrically conductive plug leading through the intermediate oxide. A layer system of a conductive oxygen diffusion barrier and a conductive adhesion layer is deposited directly below the bottom capacitor electrode, and the adhesion layer and the overlying oxygen diffusion barrier are deposited directly into the contact hole and form the plug at least in the region lying directly below the bottom capacitor electrode.

    14.
    发明专利
    未知

    公开(公告)号：DE10121657A1

    公开(公告)日：2002-11-28

    申请号：DE10121657

    申请日：2001-05-03

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HARTNER WALTER ,  GABRIC ZVONIMIR ,  KROENKE MATTHIAS ,  SCHINDLER GUENTHER

    IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L23/00 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L27/11502 ,  H01L21/314

    Abstract: The invention relates to a microelectronic structure which provides improved protection of a hydrogen-sensitive dielectric against hydrogen contamination. According to the invention, the hydrogen sensitive dielectric ( 14 ) is covered at lest by an intermediate oxide ( 18 ), where material thickness is at lest five times the thickness of the hydrogen-sensitive dielectric. The intermediate oxide ( 18 ) simultaneously acts as an internal dielectric and is metabolized on its surface for this purpose. The intermediate oxide ( 18 ), which has a sufficient thickness absorbers the hydrogen that may be released during the deposition of a hydrogen barrier layer ( 22, 26 ), thus protecting the hydrogen-sensitive dielectric ( 14 ).

    15.
    发明专利
    未知

    公开(公告)号：DE102005042071A1

    公开(公告)日：2007-03-08

    申请号：DE102005042071

    申请日：2005-08-31

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KROENKE MATTHIAS ,  OFFENBERG DIRK

    IPC: H01L21/8242

    Abstract: A semiconductor structure is fabricated to have a transistor cell region and a connection region. The transistors both of a transistor cell region and of a connection region are coated with a first oxide layer, the layer thickness of the first oxide layer being dimensioned in such a way that a gap region in each case remains present between the adjacent transistors in the transistor cell region. A sacrificial structure is subsequently applied between at least two adjacent transistors of the transistor cell region in the gap region. At least one gap region in each case remains free between two adjacent sacrificial structures. A second oxide layer is applied to the sacrificial structures and the first oxide layer. The first and second oxide layers are subjected to an etching step in which at least one spacer having a predetermined spacer width is formed on the side edges of at least one transistor of the connection region, the spacer being formed by the first and second oxide layers and the spacer width being determined by the layer thickness of the first and second oxide layers and also by the etching step.

    Production of a memory component, with a contact hole plane, uses a semiconductor substrate with prepared cell field and logic zones and surface gate electrode conductor paths
    18.
    发明专利
    Production of a memory component, with a contact hole plane, uses a semiconductor substrate with prepared cell field and logic zones and surface gate electrode conductor paths 未知

    公开(公告)号：DE102004020935B3

    公开(公告)日：2005-09-01

    申请号：DE102004020935

    申请日：2004-04-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GRAF WERNER ,  KROENKE MATTHIAS

    IPC: H01L21/283 ,  H01L21/768 ,  H01L21/8242

    Abstract: To produce a contact hole plane, in a memory component, a semiconductor substrate (10) is prepared with a cell field zone (101) and a logic zone (102) together with surface gate electrode conductor paths (11,12) under a covering layer (113,123), and an oxide layer (13) is applied. A block mask (14) at the cell fields is used for anisotropic etching of the oxide layer to free the semiconductor surface and covering layer at the logic zone, and the mask is removed. A second oxide layer is applied forming a sacrifice layer over the conductor paths, and a mask layer is deposited and structured to give openings for the bit conductor contacts for the contact openings. An anisotropic etching of the sacrifice layer forms blocks over the contact openings and the mask layer is removed. Etching of the conductor paths and semiconductor surface at the blocks gives them side covers from the two oxide layers. A filling layer is between the blocks, the sacrifice layer blocks are removed at the filling layer, and the contact openings are filled with a conductive material.

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