公开(公告)号：DE60308703T2

公开(公告)日：2007-08-23

申请号：DE60308703

申请日：2003-12-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KUZMENKA MAKSIM

IPC: H03H1/00 ,  H01L23/50 ,  H03H7/09 ,  H05K1/02

Abstract: A circuit comprises a first supply line (506) and a second supply line (508). A capacitor (146) is arranged between the first supply line (506) and the second supply line (508). The first supply line (506) and the second supply line (508) are inductively coupled, such that a switching current (572) on the second supply line (506) induces a compensating current (574) into the first supply line (508). The compensating current (574) compensates the switching current (572) by flowing from the second supply line (508) over the capacitor (146) into the first supply line (506).

公开(公告)号：SG127695A1

公开(公告)日：2006-12-29

申请号：SG200303513

申请日：2003-06-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUCKERBAUER HERMANN ,  KUZMENKA MAKSIM

IPC: H01R12/16 ,  H05K1/14

公开(公告)号：DE10339770A1

公开(公告)日：2005-03-31

申请号：DE10339770

申请日：2003-08-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： THOMAS JOCHEN ,  GRAFE JUERGEN ,  WENNEMUTH INGO ,  GOSPODINOVA-DALTCHEVA MINKA ,  KUZMENKA MAKSIM

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/50

Abstract: The FBGA (fine pitch ball grid array) connection device (5) is for face-down integrated circuit chips (6). It has balls of solder (14) acting as electrical contacts on the underside of the chip. The balls are in contact with through-connectors (13) under a copper layer (18) and the chip. The connectors extend through two substrate plates (1,2). A central bonding channel extends through holes in the substrate. It consists of a stepped diameter cast mass of insulating material (16) containing bridging wires (10). The chip is encapsulated in a molding compound (17).

公开(公告)号：DE10330811A1

公开(公告)日：2005-02-17

申请号：DE10330811

申请日：2003-07-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JAKOBS ANDREAS ,  RUCKERBAUER HERMANN ,  KUZMENKA MAKSIM

IPC: G11C5/06 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/4063

公开(公告)号：DE10323415A1

公开(公告)日：2004-12-30

申请号：DE10323415

申请日：2003-05-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRAUN GEORG ,  RUCKERBAUER HERMANN ,  KUZMENKA MAKSIM ,  RAGHURAM SIVA

IPC: G06F13/16 ,  G11C7/10 ,  G11C7/00

Abstract: The data storage arrangement has a control unit and a memory. Data, control, and address signals can be transmitted via data signal lines between the control device and the memory. If the total number of data signal lines is less than the total number of lines needed for transmission of the control and address signals, the arrangement has more than one memory. The number of memories is selected such that the total number of data lines is the same as the total number of lines needed to transmit the control and address signals.

公开(公告)号：DE10302128B3

公开(公告)日：2004-09-09

申请号：DE10302128

申请日：2003-01-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KUZMENKA MAKSIM ,  KIEHL OLIVER

IPC: G11C7/10 ,  G11C11/4093

Abstract: An order address signal (2) is fed to the negative input of a first receiver comparator (51) in the buffer storage circuit (1). A reference signal (Vref) is fed to the positive input. A timing signal (3) is fed to the positive and negative inputs of a second receiver comparator (52). The outputs of the comparators are connected to delay switching networks (71,72). A reference signal (4) and a feedback signal (11) are fed to a delay detector switch which produces signals (DELTAt var) to control the variable delay times. The delay switching networks are connected to first and second output buffer amplifiers. The amplifier outputs go to a reference conductor net (9) connected to parallel capacitors (10) and a signal conductor net connected to inputs of DRAM (Dynamic Random Access Memory) chips (13).

公开(公告)号：DE10229120B4

公开(公告)日：2004-05-27

申请号：DE10229120

申请日：2002-06-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUCKERBAUER HERMANN ,  KUZMENKA MAKSIM

IPC: H05K1/14 ,  G06F1/16 ,  H05K7/14

公开(公告)号：DE10157836A1

公开(公告)日：2003-06-12

申请号：DE10157836

申请日：2001-11-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KUZMENKA MAKSIM

IPC: G06F1/10 ,  G11C8/00 ,  H03L7/06 ,  H05K1/00 ,  H05K1/16 ,  G11C7/22

Abstract: A device for distributing a signal, in particular a clock signal or a command/address signal from a signal source to a plurality of circuit units, includes a transformer. The transformer has a primary winding receiving the signal from the signal source. Further, the transformer includes a plurality of secondary windings, which are arranged to interact with the primary winding to transfer the signal to the circuit units.

公开(公告)号：DE60308703D1

公开(公告)日：2006-11-09

申请号：DE60308703

申请日：2003-12-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KUZMENKA MAKSIM

IPC: H03H1/00 ,  H01L23/50 ,  H03H7/09 ,  H05K1/02

Abstract: A circuit comprises a first supply line (506) and a second supply line (508). A capacitor (146) is arranged between the first supply line (506) and the second supply line (508). The first supply line (506) and the second supply line (508) are inductively coupled, such that a switching current (572) on the second supply line (506) induces a compensating current (574) into the first supply line (508). The compensating current (574) compensates the switching current (572) by flowing from the second supply line (508) over the capacitor (146) into the first supply line (506).

公开(公告)号：DE60307834D1

公开(公告)日：2006-10-05

申请号：DE60307834

申请日：2003-08-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KUZMENKA MAKSIM

IPC: G06F13/40 ,  G11C7/10 ,  H03K17/80 ,  H03K17/81