公开(公告)号：GB2372841B

公开(公告)日：2004-09-29

申请号：GB0125220

申请日：2001-10-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DIETRICH STEFAN ,  HEYNE PATRICK ,  MARX THILO ,  SCHOENIGER SABINE ,  SOMMER MICHAEL ,  HEIN THOMAS ,  MARKERT MICHAEL ,  PARTSCH TORSTEN ,  SCHROEGMEIER PETER ,  WEIS CHRISTIAN

IPC: H02M3/07

公开(公告)号：DE50100864D1

公开(公告)日：2003-12-04

申请号：DE50100864

申请日：2001-08-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DIETRICH DR ,  HEIN THOMAS ,  HEYNE PATRICK ,  MARKERT MICHAEL ,  MARX THILO ,  PARTSCH TORSTEN ,  SCHOENIGER SABINE ,  SCHROEGMEIER PETER ,  SOMMER MICHAEL ,  WEIS CHRISTIAN

IPC: H03K5/00 ,  H03K5/13 ,  H03K5/133

Abstract: The circuit has input and output connections (1,2), first and second signal paths (3,4) with different delay times, a multiplexer (6), a drive circuit (5) with first and second programmable paths and transistors controled by complementary control signals and connected to nodes commonly connected to a multiplexer control input. Only one programmable path is programmed to be conducting and the other to be non-conducting.

公开(公告)号：DE10203152C1

公开(公告)日：2003-10-23

申请号：DE10203152

申请日：2002-01-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHROEGMEIER PETER ,  DIETRICH STEFAN ,  ACHARYA PRAMOD ,  KIESER SABINE ,  GRAESSER URSULA ,  SCHNEIDER HELMUT ,  MARKERT MICHAEL

IPC: G11C8/08 ,  H01L27/108 ,  H01L27/105

Abstract: The memory device (100) has at least one memory module and associated word decoder block and at least one driver transistor pair (101a,101b), coupled to the word decoder block at their gates (104) in a ring structure (RDC). The sources (102) of the driver transistor pair lie outside the ring structure and have a common diffusion zone, the drains lying within the ring structure and coupled to at least one memory row selection line (106a,106b), adjacent selection lines coupled via a coupling transistor (105) receiving the same gate signal as the driver transistor pair.

公开(公告)号：DE10154066A1

公开(公告)日：2003-05-22

申请号：DE10154066

申请日：2001-11-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHROEGMEIER PETER ,  DIETRICH STEFAN ,  KIESER SABINE ,  WEIS CHRISTIAN ,  MARKERT MICHAEL ,  HEIN THOMAS

IPC: G11C7/06 ,  G11C11/408 ,  G11C11/4091 ,  G11C7/10

Abstract: The memory has a cell field with row lines for cell selection, column lines for reading or writing data signals via read-write amplifiers and column selection lines for activating the amplifiers. Each cell group has a defined number of row and column addresses and corresponding connection pads. A control circuit activates at least 2 different column selection lines with one column address and one of the column lines for 2 or more column addresses. The device has a memory cell field with row lines (WL1-4) for selecting cells and column lines for reading or writing data signals via read-write amplifiers (11,12,21,22) and column selection lines (CSL1,2) for activating the amplifiers. Each cell group has a defined number of row and column addresses and corresponding connection pads (15,25). A control circuit activates at least two different column selection lines with one column address and one of the column lines for two or more column addresses. AN Independent claim is also included for the following: a method of operating an inventive device.

公开(公告)号：GB2372841A

公开(公告)日：2002-09-04

申请号：GB0125220

申请日：2001-10-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DIETRICH STEFAN ,  HEYNE PATRICK ,  MARX THILO ,  SCHOENIGER SABINE ,  SOMMER MICHAEL ,  HEIN THOMAS ,  MARKERT MICHAEL ,  PARTSCH TORSTEN ,  SCHROEGMEIER PETER ,  WEIS CHRISTIAN

IPC: H02M3/07

Abstract: A voltage pump for generating an increased output voltage VPP has a turn-on control comprising a transistor 1 connected between a connection 3 for a supply voltage VEXT and a connection 4 for tapping-off the increased output voltage VPP. After the voltage pump 7 starts to operate, the increased output voltage VPP is decoupled from the supply voltage VEXT by the transistor 1. A switch 2 conveys the higher of the output voltage or supply voltage VPP, VEXT to the substrate connection and the gate connection of the transistor 1. The turn-on control makes possible an early provision of an increased output voltage with safe start-up operation of the voltage pump 7, only a small circuit complexity being necessary.

公开(公告)号：DE10021776A1

公开(公告)日：2001-11-22

申请号：DE10021776

申请日：2000-05-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FISCHER HELMUT ,  SCHNEIDER HELMUT ,  SCHOENINGER SABINE ,  MARKERT MICHAEL

IPC: G11C7/06 ,  G11C11/4091

Abstract: At least one of the drive transistors (N1, P1) is arranged with its doping areas between the associated NMOS or PMOS transistors of the read/write amplifiers (N2, N3, P2, P3), and the gate of these drive transistors (N1, P1) is constructed as a two-strip gate (N111, P111).

公开(公告)号：DE50114463D1

公开(公告)日：2008-12-18

申请号：DE50114463

申请日：2001-09-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DIETRICH STEFAN DR ,  HEYNE PATRICK ,  MARX THILO ,  SCHOENIGER SABINE ,  SOMMER MICHAEL ,  HEIN THOMAS ,  MARKERT MICHAEL ,  PARTSCH TORSTEN ,  SCHROEGMEIER PETER ,  WEIS CHRISTIAN

IPC: G01R31/28 ,  G11C29/00 ,  G06F11/22 ,  G11C11/401 ,  G11C11/407 ,  G11C29/34 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04

Abstract: Integrated circuits, in particular memory chips of the DDR SDRAM type, are tested in a parallel manner. In order to prevent the circuits from being driven relative to one another during a test operation, an input terminal that is already connected to a channel of an automatic test machine anyway is connected to a switching device, by which the output drivers can be turned off in a manner dependent on the control signal that can be fed in at the input terminal. The switching device preferably contains a demultiplexer and also a multiplexer. The demultiplexer can be driven by a test control signal that is additionally generated besides the test control signal. The input terminal is connected to a tester channel anyway during test operation, with the result that no additional external outlay arises.

公开(公告)号：DE10154066B4

公开(公告)日：2004-02-12

申请号：DE10154066

申请日：2001-11-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHROEGMEIER PETER ,  DIETRICH STEFAN ,  KIESER SABINE ,  WEIS CHRISTIAN ,  MARKERT MICHAEL ,  HEIN THOMAS

IPC: G11C7/06 ,  G11C11/408 ,  G11C11/4091 ,  G11C7/10

Abstract: The memory has a cell field with row lines for cell selection, column lines for reading or writing data signals via read-write amplifiers and column selection lines for activating the amplifiers. Each cell group has a defined number of row and column addresses and corresponding connection pads. A control circuit activates at least 2 different column selection lines with one column address and one of the column lines for 2 or more column addresses. The device has a memory cell field with row lines (WL1-4) for selecting cells and column lines for reading or writing data signals via read-write amplifiers (11,12,21,22) and column selection lines (CSL1,2) for activating the amplifiers. Each cell group has a defined number of row and column addresses and corresponding connection pads (15,25). A control circuit activates at least two different column selection lines with one column address and one of the column lines for two or more column addresses. AN Independent claim is also included for the following: a method of operating an inventive device.

公开(公告)号：DE10051937A1

公开(公告)日：2002-05-08

申请号：DE10051937

申请日：2000-10-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HEYNE PATRICK ,  SOMMER MICHAEL ,  SCHROEGMEIER PETER ,  DIETRICH STEFAN ,  SCHOENIGER SABINE ,  WEIS CHRISTIAN ,  MARX THILO ,  MARKERT MICHAEL ,  PARTSCH TORSTEN ,  HEIN THOMAS

IPC: H03K5/00 ,  H03K5/13 ,  H03K5/133 ,  H03K5/14

Abstract: The circuit has input and output connections (1,2), first and second signal paths (3,4) with different delay times, a multiplexer (6), a drive circuit (5) with first and second programmable paths and transistors controled by complementary control signals and connected to nodes commonly connected to a multiplexer control input. Only one programmable path is programmed to be conducting and the other to be non-conducting.