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    11.
    发明专利
    未知

    公开(公告)号：DE19957123B4

    公开(公告)日：2006-11-16

    申请号：DE19957123

    申请日：1999-11-26

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BENZINGER HERBERT ,  RICHTER FRANK

    IPC: H01L21/8242 ,  H01L27/108

    Abstract: A DRAM cell configuration is described in which a memory cell in each case has a storage capacitor and a read-out transistor. For connecting to the read-out transistor, a buried strap contact is produced by outdiffusion of dopants from the electrode of the storage capacitor. The buried strap contact is superposed by the implantations of the source/drain region of the read-out transistor, so that the implantations of the source/drain region form the boundary of the space charge zone of a p/n junction of the memory cell.

    12.
    发明专利
    未知

    公开(公告)号：DE10131237B8

    公开(公告)日：2006-08-10

    申请号：DE10131237

    申请日：2001-06-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： TEMMLER DIETMAR ,  RICHTER FRANK ,  POPP MARTIN ,  WICH-GLASEN ANDREAS

    IPC: H01L29/78 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06

    Abstract: A transistor is provided which advantageously utilizes a part of the area which, in conventional transistors, is provided for the isolation between the transistors. In this case, the channel width can be enlarged in a self-aligned manner without the risk of short circuits. The field-effect transistor according to the invention has the advantage that it is possible to ensure a significant increase in the effective channel width for the forward current ION compared with previously used, conventional transistor structures, without having to accept a reduction of the integration density that can be attained. Thus, by way of example, the forward current I ON can be increased by up to 50%, without having to alter the arrangement of the active regions or of the trench isolation.

    16.
    发明专利
    未知

    公开(公告)号：DE10153619B4

    公开(公告)日：2004-07-29

    申请号：DE10153619

    申请日：2001-10-31

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GRUENING VON SCHWERIN ULRIKE ,  RUF ALEXANDER ,  RICHTER FRANK ,  BEWERSDORFF-SARLETTE ULRIKE

    IPC: H01L21/336 ,  H01L21/265 ,  H01L21/28 ,  H01L29/423

    Abstract: The production of a gate layer stack for an integrated circuit configuration comprises depositing a lower gate layer on the gate oxide layer formed on a semiconductor substrate; depositing and patterning an upper gate layer; patterning an upper part of a layer thickness of the lower gate layer; depositing a protective layer; and further patterning until lower part of layer thickness is patterned. The production of a gate layer stack (10) for an integrated circuit configuration comprises depositing a lower gate layer on the gate oxide layer (2) formed on a semiconductor substrate (1); depositing an upper gate layer having a higher electrical conductivity than the lower gate layer above the lower gate layer; patterning at least the upper gate layer; patterning an upper part of a layer thickness of the lower gate layer; depositing a protective layer at least onto sidewalls (8) of the patterned upper gate layer and of the upper part of the layer thickness of the lower gate layer resulting in a formation of sidewall coverings (9), the lower gate layer, upper gate layer, and the protective layer defining the gate layer stack; and further patterning the gate layer stack at least until the gate oxide layer is reached and the lower gate layer is patterned only in a lower part of the layer thickness.

    Production of memory cell array, e.g. dynamic random access memory, includes stages for contacting superimposed selective transistor and memory capacitor
    17.
    发明专利
    Production of memory cell array, e.g. dynamic random access memory, includes stages for contacting superimposed selective transistor and memory capacitor 未知

    公开(公告)号：DE10126604C1

    公开(公告)日：2002-12-19

    申请号：DE10126604

    申请日：2001-05-31

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： TEMMLER DIETMAR ,  RICHTER FRANK

    IPC: G11C7/00 ,  H01L21/8242 ,  H01L27/108

    Abstract: Memory cell array production involves: forming a contact hole in the semiconductor between 2 adjacent cells to expose part of the capacitor trench fillings and a conducting zone of the selective transistor; filling the hole with conductor; forming an insulation hole in the contact hole to divide the conductor layer into 2 sub-zones; and filling the hole with insulation. Production of a memory cell array involves: (A) forming a trench capacitor for each cell in a semiconductor substrate with electrically conducting trench filling; (B) producing a semiconductor layer over the trench capacitors; and (C) forming a selective transistor for each cell with 2 conductive zones in the surface of the semiconductor layer, a channel zone between these and an insulated conducting layer over the whole as word lead. The novel features are that (D) a contact hole is formed in the semiconductor layer between 2 adjacent memory cells, so that each hole exposes part of the trench filling of the 2 capacitors and also a conducting zone belonging to the selective transistor in the semiconductor layer; (E) this contact hole is filled with an electrically conducting layer; (F) an insulation hole is formed in the contact hole at least to the upper edge of the trench capacitor, so that the conducting layer in this hole is divided into 2 sub-zones, each connecting the trench filling to the electrically conducting zone of the selective transistor; and (G) the insulating hole is filled with an insulating layer, so that both sub-zones of the conducting layer in the contact are insulated from one another electrically. An Independent claim is also included for a memory cell array of this type on a semiconductor wafer, which has a number of memory cells arranged in a matrix, parallel bit leads and parallel word leads, perpendicular to the bit leads.

    18.
    发明专利
    未知

    公开(公告)号：DE10131276B4

    公开(公告)日：2007-08-02

    申请号：DE10131276

    申请日：2001-06-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： TEMMLER DIETMAR ,  RICHTER FRANK ,  POPP MARTIN ,  WICH-GLASEN ANDREAS

    IPC: H01L29/423 ,  H01L29/78 ,  H01L21/336 ,  H01L29/49 ,  H01L29/786

    Abstract: The invention relates to a field effect transistor in which the planar channel region on the upper surface of the elevation is extended in width by means of additional vertical channel regions on the lateral surfaces of the elevation. Said additional vertical channel regions connect directly to the planar channel region (vertical extended channel regions). Said field effect transistor has the advantage that a significant increase in the effective channel width for the current flow I ON can be guaranteed relative to conventional transistor structures used up until the present, without having to accept a reduction in the achievable integration density. Said field effect transistor furthermore has a low reverse current I OFF . The above advantages are achieved without the thickness of the gate insulators up to the region of the charge transfer tunnels having to be reduced or a reduced stability.

    20.
    发明专利
    未知

    公开(公告)号：DE10131237A1

    公开(公告)日：2003-01-23

    申请号：DE10131237

    申请日：2001-06-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： TEMMLER DIETMAR ,  RICHTER FRANK ,  POPP MARTIN ,  WICH-GLASEN ANDREAS

    IPC: H01L29/78 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06

    Abstract: The invention relates to a transistor that advantageously uses a portion of the surface, which is provided in conventional transistors for insulating the transistors. This enables the enlargement of the channel width to self-adjust without the risk of short-circuits. The inventive field effect transistor is advantageous in that a distinct increase in the channel width that is active for the forward current ION can, compared to conventional transistor structures used up to now, be guaranteed without having to accept a decrease in the attainable integration density. This permits, for example, the forward current ION to increase by 50 % without having to modify the arrangement of the active regions or of the trench insulation.

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