公开(公告)号：DE10258199B4

公开(公告)日：2005-03-10

申请号：DE10258199

申请日：2002-12-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STOCKEN CHRISTIAN ,  PROELL MANFRED ,  DOBLER MANFRED ,  RESCH GERALD

IPC: G11C29/02 ,  G11C29/00

Abstract: A circuit arrangement can have a number of integrated circuit components, which are arranged on a carrier substrate. A reception circuit for receiving a control signal can be coupled to one of the connection pads on the input side and can be connected to each of the circuit components on the output side. A bridging circuit controlled by a test mode signal can electrically bridge the reception circuit. In a testing method, a plurality of connection pads can be connected to a first potential and at least one of the connection pads can be connected to a second potential. The bridging circuit can be activated and the current measured, by a test arrangement, at the at least one of the connection pads. Inspection for leakage currents in connections between input-side reception circuits and the circuit components can be measured.

公开(公告)号：DE10258199A1

公开(公告)日：2004-07-15

申请号：DE10258199

申请日：2002-12-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STOCKEN CHRISTIAN ,  PROELL MANFRED ,  DOBLER MANFRED ,  RESCH GERALD

IPC: G11C29/02 ,  G11C29/00

Abstract: A circuit arrangement can have a number of integrated circuit components, which are arranged on a carrier substrate. A reception circuit for receiving a control signal can be coupled to one of the connection pads on the input side and can be connected to each of the circuit components on the output side. A bridging circuit controlled by a test mode signal can electrically bridge the reception circuit. In a testing method, a plurality of connection pads can be connected to a first potential and at least one of the connection pads can be connected to a second potential. The bridging circuit can be activated and the current measured, by a test arrangement, at the at least one of the connection pads. Inspection for leakage currents in connections between input-side reception circuits and the circuit components can be measured.

公开(公告)号：DE102004021267B4

公开(公告)日：2008-04-17

申请号：DE102004021267

申请日：2004-04-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STOCKEN CHRISTIAN

IPC: G11C29/42 ,  G11C29/00

公开(公告)号：DE10152916B4

公开(公告)日：2006-11-30

申请号：DE10152916

申请日：2001-10-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STOCKEN CHRISTIAN ,  CORDES ERIC ,  WIRTH NORBERT ,  TASKIN NAZIF

IPC: G06F12/00 ,  G11C5/00 ,  G11C8/18

公开(公告)号：DE10301480B4

公开(公告)日：2006-04-20

申请号：DE10301480

申请日：2003-01-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STOCKEN CHRISTIAN ,  DOBLER MANFRED ,  EGGERS GEORG

IPC: H01L23/50 ,  H01L21/50 ,  H01L21/60 ,  H01L23/495 ,  H05K3/34

Abstract: The method involves one or more stamping process steps in which at least one pin is stamped out of a base body, especially a lead frame. The pin or a section of the pin is coated with a separate metal coating only after final stamping out of the pin. The end face of the outer end section of the pin is also coated with the metal coating. Independent claims are also included for the following: (a) a housing, especially for semiconducting components (b) and a semiconducting component pin.

公开(公告)号：DE10293994D2

公开(公告)日：2004-07-22

申请号：DE10293994

申请日：2002-08-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CORDES ERIC ,  EGGERS GEORG ERHARD ,  LUEPKE JENS ,  STOCKEN CHRISTIAN

IPC: G01R31/28 ,  G11C7/10 ,  G11C11/401 ,  G11C29/50 ,  G11C29/56 ,  G11C29/00

Abstract: A test method for a semiconductor memory device having a bidirectional data strobe terminal for a data strobe signal, and having at least one data terminal for a data signal at a test apparatus, which can at least generate data strobe and data signals and also transfer and evaluate data signals. The memory device is connected to a test apparatus, which generates data strobe and data signals, and transfers and evaluates data signals. In the course of the test using the data strobe and data signals, data are transferred from the first semiconductor memory device to a second semiconductor memory device of identical type and are evaluated after a read-out from the second semiconductor memory device by the test apparatus.

公开(公告)号：DE10143764A1

公开(公告)日：2003-03-27

申请号：DE10143764

申请日：2001-09-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STOCKEN CHRISTIAN ,  CORDES ERIC ,  EGGERS GEORG ,  DOBLER MANFRED

IPC: H01L21/60 ,  H01L21/607 ,  H01L23/13 ,  H05K3/34 ,  H01L21/58

Abstract: During attachment, the temperature of memory components (especially micro-capacitors) of the chip, is held below that reached during soldering in a soldering oven.

公开(公告)号：DE10161044A1

公开(公告)日：2003-03-13

申请号：DE10161044

申请日：2001-12-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STOCKEN CHRISTIAN ,  CORDES ERIC ,  WIRTH NORBERT ,  TASKIN NAZIF

IPC: H01L23/525 ,  H01L23/58

Abstract: An integrated semiconductor chip comprises a substrate (1) with a circuit (3) contact surfaces (4) connected to a chip housing (5) connections (6). An electrically switchable device (7) in a connection between the circuit and housing can be switched in to select one of many operational modes of the chip.

公开(公告)号：DE50204890D1

公开(公告)日：2005-12-15

申请号：DE50204890

申请日：2002-08-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CORDES ERIC ,  EGGERS ERHARD ,  LUEPKE JENS ,  STOCKEN CHRISTIAN

IPC: G01R31/28 ,  G11C7/10 ,  G11C11/401 ,  G11C29/50 ,  G11C29/56 ,  G11C29/00

Abstract: A test method for a semiconductor memory device having a bidirectional data strobe terminal for a data strobe signal, and having at least one data terminal for a data signal at a test apparatus, which can at least generate data strobe and data signals and also transfer and evaluate data signals. The memory device is connected to a test apparatus, which generates data strobe and data signals, and transfers and evaluates data signals. In the course of the test using the data strobe and data signals, data are transferred from the first semiconductor memory device to a second semiconductor memory device of identical type and are evaluated after a read-out from the second semiconductor memory device by the test apparatus.

公开(公告)号：DE102004051158A1

公开(公告)日：2005-06-16

申请号：DE102004051158

申请日：2004-10-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STOCKEN CHRISTIAN ,  FUNFROCK FABIEN ,  KALLSCHEUER JOCHEN ,  SOMMER MICHAEL BERNHARD

IPC: G11C7/10 ,  G11C7/20 ,  G11C8/00 ,  G11C8/12 ,  G11C11/4072 ,  G11C11/408 ,  G06F12/06

Abstract: An integrated semiconductor memory device includes a first memory zone, a second memory zone, first address connections and a second address connection. A second address signal present at the second address connection specifies the access to the first or second memory zone, whereas it is specified via first address signals at the first address connections which memory cell is accessed within the first or second memory zone. In a first memory configuration, all address connections are driven externally with address signals and the access to a memory cell in the first or second memory zone is controlled. In a second memory configuration, only the first address connections are driven externally whereas a signaling bit in a mode register regulates the access to the first or second memory zone. This provides for access to the second memory zone even if there is no possibility of externally driving the second address connection.