公开(公告)号：DE10143936A1

公开(公告)日：2003-01-09

申请号：DE10143936

申请日：2001-09-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BIRNER ALBERT ,  LUETZEN JOERN ,  GOLDBACH MATTHIAS ,  BREUER STEFFEN ,  SCHUMANN DIRK

IPC: H01L21/8242 ,  H01L27/12 ,  H01L21/84 ,  H01L21/336

Abstract: Production of a layer stack made from a silicon oxide layer and a monocrystalline silicon layer on a substrate comprises: forming mesopores in the surface region of substrate; oxidizing the surface to form silicon oxide and bar regions; exposing the bar regions facing away from the substrate; and selectively epitaxially growing the silicon on exposed bar regions opposite the silicon oxide regions. Production of a layer stack made from a silicon oxide layer (11) and a monocrystalline silicon layer (12) on a substrate (2) comprises: forming mesopores (10) in the surface region (3) of the substrate; oxidizing the surface to form silicon oxide and bar regions (22) made from single crystalline silicon which remain between neighboring mesopores; exposing the bar regions facing away from the substrate; and selectively epitaxially growing the silicon on the exposed bar regions opposite the silicon oxide regions. Independent claims are also included for the following: (a) a vertical transistor; and (b) a storage cell. Preferred Features: The process further comprises heat treating to oxidize the silicon bar regions. The bar regions have a diameter of 5-15 nm. The bar regions are exposed by wet chemical etching. The silicon oxide layer is 10-50 nm thick.

公开(公告)号：DE10055712A1

公开(公告)日：2002-05-23

申请号：DE10055712

申请日：2000-11-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BIRNER ALBERT ,  GOLDBACH MATTHIAS ,  SCHUMANN DIRK

IPC: C25F3/12 ,  H01L21/3063 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108 ,  H01L29/92

Abstract: Production of trench capacitors in a p-doped silicon layer comprises: (i) preparing a p-doped silicon layer having a prescribed resistivity; (ii) producing starting seeds on the front side of the silicon layer; (iii) applying an electrolyte to the front side of the silicon layer; (iv) applying an electrical voltage between the rear side of the silicon layer and the electrolyte so that an electric current with a given current density flows in the layer and trenches are produced; (v) forming a first electrode (2-24) in the trench; (vi) applying a capacitor dielectric (2-26) to the first electrode; and (vii) producing as second electrode (2-28) in the trench (2-22). Preferred Features: The p-doped silicon layer is a silicon wafer or part of a p-doped silicon wafer or lies on a p-doped silicon wafer. The p-doped silicon layer has a resistivity of less than 2 ohm.cm, preferably 0.3 ohm.cm.

公开(公告)号：DE50205437D1

公开(公告)日：2006-02-02

申请号：DE50205437

申请日：2002-02-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SELL BERNHARD ,  SAENGER ANNETTE ,  SCHUMANN DIRK

IPC: G11C15/00 ,  H01L21/02 ,  H01L21/285 ,  H01L21/316 ,  H01L21/8242 ,  H01L27/108

Abstract: The present invention relates to a novel method for fabricating a storage capacitor designed as a trench or a stacked capacitor and is used in particular in a DRAM memory cell. The method includes steps of forming a lower, metallic capacitor electrode, a storage dielectric and an upper capacitor electrode. The lower, metallic capacitor electrode is formed in a self-aligned manner on a silicon base material in such a way that uncovered silicon regions are first produced at locations at which the lower capacitor electrode will be formed, and then metal silicide is selectively formed on the uncovered silicon regions.

公开(公告)号：DE10243380A1

公开(公告)日：2004-04-01

申请号：DE10243380

申请日：2002-09-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOEBEL BERND ,  MOLL PETER ,  SCHUMANN DIRK ,  SEIDL HARALD

IPC: H01L20060101 ,  H01L21/768 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/108

公开(公告)号：DE50205651D1

公开(公告)日：2006-04-06

申请号：DE50205651

申请日：2002-02-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CAPPELLANI ANNALISA ,  DITTMAR LUDWIG ,  SCHUMANN DIRK

IPC: H01L21/28 ,  H01L21/3065 ,  H01L21/265 ,  H01L21/3213 ,  H01L21/336 ,  H01L29/78

Abstract: A gate layer stack formed with at least two layers is firstly patterned anisotropically and then thelower layer is etched. An isotropic, preferably selective etching step effects a lateral undercutting, i.e. removal of the lower layer as far as the predetermined channel length to form a dimensionally accurate T-gate transistor with a very short channel length.

公开(公告)号：DE10142307A1

公开(公告)日：2003-03-27

申请号：DE10142307

申请日：2001-08-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CAPPELLANI ANNALISA ,  CURELLO GIUSEPPE ,  SCHUMANN DIRK

IPC: H01L21/265 ,  H01L21/266 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L29/06

Abstract: A depression is produced into the channel region (2-3) of the semiconductor substrate (2-0). This lies below surrounding regions of the substrate. A gate insulator (2-24) is produced on the surface of the channel region and a gate electrode (2-26) is then deposited upon it. In immediately surrounding regions of the substrate, diffused regions are produced to form the source (2-52) and drain (2-53).

公开(公告)号：DE10143650A1

公开(公告)日：2003-03-13

申请号：DE10143650

申请日：2001-09-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOEBEL BERND ,  STEINHOEGL WERNER ,  KERSCH ALFRED ,  GUTSCHE MARTIN ,  SEIDL HARALD ,  LUETZEN JOERN ,  POPP MARTIN ,  SCHUMANN DIRK

IPC: H01L21/8242 ,  H01L27/108

Abstract: A semiconductor memory cell has trenches (25,50) in a substrate (15) having a capacitor (30) and long trenches having spacer wordlines with an active region between them having a vertical select transistor. Conductive bridges between wordlines in a trench are less than half as thick as the trench width. An Independent claim is also included for a process for making the above memory.

公开(公告)号：DE10109218A1

公开(公告)日：2002-06-27

申请号：DE10109218

申请日：2001-02-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SELL BERNHARD ,  SAENGER ANNETTE ,  SCHUMANN DIRK

IPC: H01L21/02 ,  H01L21/285 ,  H01L21/316 ,  H01L21/8242 ,  H01L27/108

Abstract: Production of a storage capacitor comprises forming a lower metallic capacitor electrode (13), a storage dielectric (14) and an upper capacitor electrode (15). The lower capacitor electrode is formed on a silicon base material (1) in a self-adjusting manner so that exposed silicon regions are formed. A metal silicide is then selectively formed on the exposed regions. Preferred Features: The metal is W, Ti, Mo, Ta, Co, Ni, Pt, Pd or a rare earth. The step of selectively forming a metal silicide on the exposed silicon regions comprises depositing a metal (12), heat treating at a prescribed temperature, and selectively removing unreacted metal. The heat treatment step is carried out at 600-1000 deg C in a nitrogen atmosphere.

公开(公告)号：DE10021871A1

公开(公告)日：2001-11-15

申请号：DE10021871

申请日：2000-05-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CAPPELLANI ANNALISA ,  WILLER JOSEF ,  SCHUMANN DIRK

IPC: H01L21/265 ,  H01L21/28 ,  H01L29/49 ,  H01L21/283

Abstract: Production of a barrier layer in an electronic component comprises implanting atoms which form the barrier layer in a substrate material; applying a metal layer to the substrate material; and partially reacting the substrate material, the atoms and the metal layer to form the barrier layer. Preferred Features: The atoms used in the implanting step are nitrogen or born atoms. The substrate material is silicon, gallium-arsenide or germanium. The metal layer is made from W, Mo, Ta, Re, Ti, Zr, Hf, Nb and/or Ru.

公开(公告)号：DE50014010D1

公开(公告)日：2007-03-15

申请号：DE50014010

申请日：2000-09-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHUMANN DIRK ,  SELL BERNHARD ,  WILLER JOSEF

IPC: H01L21/00 ,  H01L21/8242 ,  H01L21/02 ,  H01L27/108