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公开(公告)号:US10522485B2
公开(公告)日:2019-12-31
申请号:US15776474
申请日:2015-12-21
Applicant: Intel IP Corporation
Inventor: Christian Geissler , Sven Albers , Georg Seidemann , Andreas Wolter , Klaus Reingruber , Thomas Wagner , Marc Dittes
IPC: H01L23/52 , H01L23/00 , H01L21/768 , H01L23/525 , H01L23/532
Abstract: An electrical device includes a redistribution layer structure, an inter-diffusing material contact structure and a vertical electrically conductive structure located between the redistribution layer structure and the inter-diffusing material contact structure. The vertical electrically conductive structure includes a diffusion barrier structure located adjacently to the inter-diffusing material contact structure. Further, the diffusion barrier structure and the redistribution layer structure comprise different lateral dimensions.
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公开(公告)号:US20190333886A1
公开(公告)日:2019-10-31
申请号:US16505307
申请日:2019-07-08
Applicant: Intel IP Corporation
Inventor: Klaus Reingruber , Andreas Wolter , Georg Seidemann , Thomas Wagner , Bernd Waidhas
Abstract: A microelectronic package with two semiconductor die coupled on opposite sides of a redistribution layer 108, and at least partially overlapping with one another. At least a first of the semiconductor die includes two sets of contacts, the first group of contacts arranged at a lesser pitch relative to one another than are a second group of contacts. The first group of contacts at the larger pitch are placed to engage contacts in a redistribution layer 108. The second group of contacts at the lesser pitch are placed to engage respective contacts at the same pitch on the second semiconductor die.
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公开(公告)号:US10347558B2
公开(公告)日:2019-07-09
申请号:US15748475
申请日:2015-08-31
Applicant: INTEL IP CORPORATION
Inventor: Christian Geissler , Georg Seidemann , Sonja Koller , Jan Proschwitz
IPC: H01L23/00 , H01L25/065 , H01L23/367 , H01L25/04 , H01L25/07 , H01L23/13 , H01L23/36 , H01L23/42 , H01L21/56 , H01L23/498
Abstract: Embodiments herein generally relate to the field of package assembly to facilitate thermal conductivity. A package may have a hanging die, and attach to a printed circuit board (PCB). The package may have an active side plane and an inactive side plane opposite the first active side plane. The package may also have a ball grid array (BGA) matrix having a height determined by a distance of a furthest point of the BGA matrix from the active side plane of the package. The package may have a hanging die attached to the active side plane of the package, the hanging die having a z-height greater than the BGA matrix height. When package is attached to the PCB, the hanging die may fit into an area on the PCB that is recessed or has been cut away, and a thermal conductive material may connect the hanging die and the PCB.
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公开(公告)号:US20190072732A1
公开(公告)日:2019-03-07
申请号:US16182450
申请日:2018-11-06
Applicant: Intel IP Corporation
Inventor: Georg Seidemann , Christian Geissler , Sven Albers , Thomas Wagner , Marc Dittes , Klaus Reingruber , Andreas Wolter , Richard Patten
CPC classification number: G02B6/428 , G02B6/12002 , G02B6/122 , G02B6/1221 , G02B6/132 , G02B6/30 , G02B6/4232 , G02B6/4238 , G02B6/43 , G02B2006/12197
Abstract: Disclosed is a package comprising a substrate having a patterned surface with an optical contact area, an optical redistribution layer (oRDL) feature, and a build-up material extending over the patterned surface of the substrate and around portions of the oRDL features. In some embodiments, the package comprises a liner sheathing the oRDL features. In some embodiments, the oRDL feature extends through openings in an outer surface of the build-up material and forms posts extending outward from the outer surface. In some embodiments, the package comprises an electrical redistribution layer (eRDL) feature, at least some portion of which overlap at least some portion of the oRDL feature. In some embodiments, the package comprises an optical fiber coupled to the oRDL features.
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公开(公告)号:US10209466B2
公开(公告)日:2019-02-19
申请号:US15089524
申请日:2016-04-02
Applicant: Intel IP Corporation
Inventor: Georg Seidemann , Christian Geissler , Sven Albers , Thomas Wagner , Marc Dittes , Klaus Reingruber , Andreas Wolter , Richard Patten
Abstract: Disclosed is a package comprising a substrate having a patterned surface with an optical contact area, an optical redistribution layer (oRDL) feature, and a build-up material extending over the patterned surface of the substrate and around portions of the oRDL features. In some embodiments, the package comprises a liner sheathing the oRDL features. In some embodiments, the oRDL feature extends through openings in an outer surface of the build-up material and forms posts extending outward from the outer surface. In some embodiments, the package comprises an electrical redistribution layer (eRDL) feature, at least some portion of which overlap at least some portion of the oRDL feature. In some embodiments, the package comprises an optical fiber coupled to the oRDL features.
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公开(公告)号:US10141265B2
公开(公告)日:2018-11-27
申请号:US15394388
申请日:2016-12-29
Applicant: Intel IP Corporation
Inventor: Bernd Waidhas , Stephan Stoeckl , Andreas Wolter , Reinhard Mahnkopf , Georg Seidemann , Thomas Wagner , Laurent Millou
IPC: H01L23/06 , H01L23/538 , H01L25/065 , H01L23/00 , H01L21/48 , H01L23/053
Abstract: A bent-bridge semiconductive apparatus includes a silicon bridge that is integral to a semiconductive device and the silicon bridge is deflected out of planarity. The silicon bridge may couple two semiconductive devices, all of which are from an integral processed die.
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公开(公告)号:US20170285280A1
公开(公告)日:2017-10-05
申请号:US15089524
申请日:2016-04-02
Applicant: Intel IP Corporation
Inventor: Georg Seidemann , Christian Geissler , Sven Albers , Thomas Wagner , Marc Dittes , Klaus Reingruber , Andreas Wolter , Richard Patten
CPC classification number: G02B6/428 , G02B6/12002 , G02B6/122 , G02B6/1221 , G02B6/132 , G02B6/30 , G02B6/4232 , G02B6/4238 , G02B6/43 , G02B2006/12197
Abstract: Disclosed is a package comprising a substrate having a patterned surface with an optical contact area, an optical redistribution layer (oRDL) feature, and a build-up material extending over the patterned surface of the substrate and around portions of the oRDL features. In some embodiments, the package comprises a liner sheathing the oRDL features. In some embodiments, the oRDL feature extends through openings in an outer surface of the build-up material and forms posts extending outward from the outer surface. In some embodiments, the package comprises an electrical redistribution layer (eRDL) feature, at least some portion of which overlap at least some portion of the oRDL feature. In some embodiments, the package comprises an optical fiber coupled to the oRDL features.
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公开(公告)号:US09209143B2
公开(公告)日:2015-12-08
申请号:US14038248
申请日:2013-09-26
Applicant: Intel IP Corporation
Inventor: Georg Seidemann , Sven Albers , Teodora Ossiander , Michael Skinner , Hans-Joachim Barth , Harald Gossner , Reinhard Mahnkopf , Christian Mueller , Wolfgang Molzer
CPC classification number: H01L24/09 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/13 , H01L24/16 , H01L24/48 , H01L24/80 , H01L24/81 , H01L25/0655 , H01L25/50 , H01L2224/03444 , H01L2224/0346 , H01L2224/03602 , H01L2224/0401 , H01L2224/04042 , H01L2224/05009 , H01L2224/05013 , H01L2224/05014 , H01L2224/05015 , H01L2224/05016 , H01L2224/05553 , H01L2224/05556 , H01L2224/05571 , H01L2224/05573 , H01L2224/0558 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/06135 , H01L2224/06155 , H01L2224/06183 , H01L2224/08054 , H01L2224/08056 , H01L2224/08057 , H01L2224/08121 , H01L2224/08137 , H01L2224/08225 , H01L2224/09135 , H01L2224/09183 , H01L2224/1134 , H01L2224/131 , H01L2224/16137 , H01L2224/48137 , H01L2224/80201 , H01L2224/80895 , H01L2224/81203 , H01L2224/94 , H01L2924/00014 , H01L2924/1434 , H01L2224/03 , H01L2924/014 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: An apparatus comprises a first integrated circuit (IC) die that includes a top layer, a bottom surface, a sidewall surface extending from a top surface of the top layer to the bottom surface, and at least one multi-surface contact pad, a second IC die including a top layer, a bottom surface, a sidewall surface extending from a top surface of the top layer to the bottom surface, and at least one multi-surface contact pad, wherein the second IC die is arranged adjacent to the first IC die, and includes an electrically conductive bond in contact with at least one of the top surface or the side surface of the multi-surface contact pad of the first IC die and the top surface of the multi-surface contact pad of the second IC die.
Abstract translation: 一种装置包括第一集成电路(IC)芯片,其包括顶层,底表面,从顶层的顶表面延伸到底表面的侧壁表面,以及至少一个多表面接触垫,第二 IC芯片包括顶层,底面,从顶层的顶表面延伸到底表面的侧壁表面,以及至少一个多表面接触焊盘,其中第二IC管芯被布置为与第一IC 并且包括与第一IC管芯的多表面接触焊盘的顶表面或侧表面中的至少一个与第二IC管芯的多表面接触焊盘的顶表面接触的导电接合 。
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19.
公开(公告)号:US08779564B1
公开(公告)日:2014-07-15
申请号:US13803143
申请日:2013-03-14
Applicant: Intel IP Corporation
Inventor: Mikael Knudsen , Thorsten Meyer , Saravana Maruthamuthu , Andreas Wolter , Georg Seidemann , Pablo Herrero , Pauli Jaervinen
IPC: H01L23/552 , H01L27/06
CPC classification number: H01L23/552 , H01L23/295 , H01L23/48 , H01L23/66 , H01L24/19 , H01L25/0655 , H01L2223/6677 , H01L2223/6688 , H01L2224/12105 , H01L2224/73267 , H01L2924/10252 , H01L2924/10253 , H01L2924/10272 , H01L2924/10329 , H01L2924/1033 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H01Q1/2283 , H01Q9/0414 , H01Q9/0421 , H01Q23/00 , H01L2924/00
Abstract: A semiconductor device may include: a chip; a chip packaging structure at least partially surrounding the chip and having a receiving region configured to receive a first capacitive coupling structure; a first capacitive coupling structure disposed in the receiving region; and a second capacitive coupling structure disposed over the first capacitive coupling structure and capacitively coupled to the first capacitive coupling structure.
Abstract translation: 半导体器件可以包括:芯片; 芯片封装结构至少部分地围绕芯片并且具有被配置为接收第一电容耦合结构的接收区域; 设置在所述接收区域中的第一电容耦合结构; 以及设置在所述第一电容耦合结构上并且电容耦合到所述第一电容耦合结构的第二电容耦合结构。
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公开(公告)号:US12249553B2
公开(公告)日:2025-03-11
申请号:US16015334
申请日:2018-06-22
Applicant: Intel IP Corporation
Inventor: Sonja Koller , Vishnu Prasad , Georg Seidemann
IPC: H01L23/367 , H01L21/56 , H01L23/31
Abstract: Present disclosure relates to IC packages with integrated thermal contacts. In some embodiments, an IC package includes a package substrate, an IC die that is coupled to the package substrate, and at least one thermal contact for coupling to at least a portion of a heat exchanger, where the thermal contact is limited to being in a region located at a periphery of the IC package. In some embodiments, thermal contacts are such that at least a portion of a heat exchanger is to be attached on the side of the IC package. In some embodiments, thermal contacts may be provided within a recessed portion at the periphery of the IC package. Providing a thermal contact at a periphery of an IC package may enable improved cooling options, especially for systems where there is no or limited space for providing conventional heat exchangers on the top of the package.
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