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公开(公告)号：DE69804562T2
公开(公告)日：2002-11-21
申请号：DE69804562
申请日：1998-09-28
Applicant: MICROCHIP TECH INC
Inventor： MITRA SUMIT K , TRIECE JOSEPH W
Abstract: A processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses in order to maximize number of directly addressable registers in the processor architecture scheme. A set of virtual address register locations associated with an indirect addressing pointer is reserved in memory. The number of virtual register address locations reserved is equal to a number of indirect addressing modes associated with the indirect addressing pointer. Each of the virtual register address locations initiates an indirect addressing mode to be used with the associated indirect addressing pointer when accessed.
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公开(公告)号：AT224558T
公开(公告)日：2002-10-15
申请号：AT98119388
申请日：1998-10-14
Applicant: MICROCHIP TECH INC
Inventor： DRAKE RODNEY J , TRIECE JOSEPH W , YACH RANDY L , BOLES BRIAN , WOJEWODA IGOR , JOHANSEN DARREL
IPC: G06F9/35
Abstract: A data pointer for generating an indirect addressing mode address within a single cycle for a selected one of a plurality of multiple indirect addressing modes. The data pointer is used with a processor architecture scheme which allows for encoding of multiple addressing modes. A data pointer register is coupled to the processor architecture scheme for storing a current address of an operand to be used in a simple indirect addressing mode. An incrementer is coupled to the data pointer register for incrementing the current address of an operand to be used in a simple indirect data addressing mode by a set number thereby generating an address of an operand to be used in an indirect addressing mode with auto preincrement. An adder is coupled to the data pointer register for combining the current address of an operand to be used in a simple indirect data addressing mode with an offset number thereby generating an address of an operand to be used in an indirect addressing mode with offset. A multiplexer circuit is coupled to an output of the data pointer register, to an output of the incrementer, and to an output of the adder for selecting a desired indirect addressing mode address.
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公开(公告)号：AT491181T
公开(公告)日：2010-12-15
申请号：AT07855101
申请日：2007-12-12
Applicant: MICROCHIP TECH INC
Inventor： PESAVENTO RODNEY J , LAHTI GREGG D , TRIECE JOSEPH W
IPC: G06F12/08
Abstract: A cache module for a central processing unit has a cache control unit coupled with a memory, and a cache memory coupled with the control unit and the memory, wherein the cache memory has a plurality of cache lines, at least one cache line of the plurality of cache lines has an address tag bit field and an associated storage area for storing instructions to be issued sequentially and at least one control bit field, wherein the control bit field is coupled with the address tag bit field to mask a predefined number of bits in the address tag bit field.
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公开(公告)号：DE69807301T2
公开(公告)日：2003-04-17
申请号：DE69807301
申请日：1998-09-18
Applicant: MICROCHIP TECH INC
Inventor： DRAKE RODNEY J , TRIECE JOSEPH W
Abstract: An instruction set for a microcontroller which has robust multiple word instructions. The instruction set has a plurality of instructions wherein the plurality of instructions comprises single word instructions and multiple word instructions. At least one bit is located in a predetermined location in all non-first words of all multiple word instructions. The bit will be decoded by the microcontroller as no operation bit if the first word of the multiple word instruction is not executed prior to execution of any succeeding words in the multiple word instruction.
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公开(公告)号：DE60000296D1
公开(公告)日：2002-09-05
申请号：DE60000296
申请日：2000-04-07
Applicant: MICROCHIP TECH INC
Inventor： BOLES EDWARD BRIAN , DRAKE RODNEY J , TRIECE JOSEPH W
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Patent Agency Ranking
公开(公告)号：DE69801355T2
公开(公告)日：2002-06-13
申请号：DE69801355
申请日：1998-10-14
Applicant: MICROCHIP TECH INC
Inventor： DRAKE J , CHIAO JENNIFER , YACH RANDY L , WOJEWODA IGOR , TRIECE JOSEPH W , ALLEN STEVE
Abstract: A system for allowing a two word instruction to be executed in a single cycle thereby allowing a processor system to increase memory space without reducing performance. A first address bus is coupled to the linearized program memory for sending addresses of instructions to be fetched to a linearized program memory. A pointer is coupled to the first address bus for storing an address location of a current instruction in the linearized program memory to be fetched and for placing the address location of the current instruction to be fetched on the first address bus. A second address bus is provided and has one end coupled to the output of the program memory and a second end coupled to the first address bus. The second address bus is used for placing an address of an operand of a second word of the two word instruction onto the first address bus after an address of an operand of a first word of the two word instruction has been placed on the first address bus. This allows the addresses of the first word and the second word to be combined to provide the full address value of the two word instruction in a single cycle.
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公开(公告)号：WO2008076892A3
公开(公告)日：2008-08-14
申请号：PCT/US2007087592
申请日：2007-12-14
Applicant: MICROCHIP TECH INC , TRIECE JOSEPH W , PESAVENTO RODNEY J , LAHTI GREGG D , DAWSON STEVEN
Inventor： TRIECE JOSEPH W , PESAVENTO RODNEY J , LAHTI GREGG D , DAWSON STEVEN
CPC classification number: G06F13/34 , G06F13/1689 , G06F13/285 , G06F13/30 , G06F13/4022
Abstract: A system has at least one bus, a central processing unit (CPU) coupled with the bus, a memory coupled with the bus, a direct memory access (DMA) controller having a plurality of DMA channels and operating independently from the CPU and being coupled with the bus, wherein for access to the bus the DMA controller is programmable in a first mode to have priority over the CPU and in a second mode in which at least one DMA channel of the DMA controller is suspended from accessing the bus.
Abstract translation: 一种系统具有至少一个总线，与总线耦合的中央处理单元（CPU），与总线耦合的存储器，具有多个DMA通道并独立于CPU操作并且耦合到其的DMA控制器的直接存储器访问（DMA）控制器 其中为了访问总线，DMA控制器在第一模式下可编程为优先于CPU，并且在第二模式下DMA控制器的至少一个DMA通道暂停访问总线。
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公开(公告)号：WO2006091468A3
公开(公告)日：2006-12-21
申请号：PCT/US2006005462
申请日：2006-02-16
Applicant: MICROCHIP TECH INC , MASGRAS CRISTIAN P , PYSKA MICHAEL , BOLES EDAWRD BRIAN , TRIECE JOSEPH W , WOJEWODA IGOR , CHEN MEI-LING
Inventor： MASGRAS CRISTIAN P , PYSKA MICHAEL , BOLES EDAWRD BRIAN , TRIECE JOSEPH W , WOJEWODA IGOR , CHEN MEI-LING
CPC classification number: G01R31/31701 , G06F11/273 , G11C29/003 , G11C29/46
Abstract: A special mode key match comparison module has N-storage elements and a special mode key match comparator. The N-storage elements accumulate a serial data stream, and then determine whether a digital device should operate in a normal user mode, in a public programming mode, or in a particular private test mode. To reduce the possibility of accidentally decoding a false test or programming mode, the data stream has a sufficiently large number of N-bits to substantially reduce the probability of a false decode. To further reduce the possibility of accidentally decoding a programming or test mode, the special mode key match comparison module may be reset if less or more than N-clocks are detected during the accumulation of the N-bit serial data stream. The special mode key match data patterns may represent a normal user mode, a public programming mode, and particular private manufacturer test modes.
Abstract translation: 特殊模式键匹配比较模块具有N个存储元件和特殊模式键匹配比较器。 N个存储元件累积串行数据流，然后确定数字设备是否应以正常用户模式，公共编程模式或特定专用测试模式运行。 为了减少意外解码错误测试或编程模式的可能性，数据流具有足够大数目的N位以显着降低错误解码的可能性。 为了进一步降低意外解码编程或测试模式的可能性，如果在N位串行数据流的累积期间检测到少于或多于N个时钟，则可以重置特殊模式密钥匹配比较模块。 特殊模式键匹配数据模式可以表示正常用户模式，公共编程模式和特定的私人制造商测试模式。
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公开(公告)号：AT534068T
公开(公告)日：2011-12-15
申请号：AT07865701
申请日：2007-12-14
Applicant: MICROCHIP TECH INC
Inventor： PESAVENTO RODNEY J , TRIECE JOSEPH W
IPC: G06F1/32
Abstract: A system has a central processing unit (CPU) operable to operate in a sleep or low power mode and in an active mode, a plurality of system components operable to operate in a sleep or low power mode and in an active mode, and a direct memory access (DMA) controller operating independently from the CPU and operable to operate in a sleep or low power mode and in an active mode, wherein the DMA controller is further operable to transfer data from and to a memory or peripheral device, wherein when the system is in a sleep or low power mode, only the DMA controller and any system component which is necessary to perform a DMA transaction are switched into active mode.
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公开(公告)号：DE69807301D1
公开(公告)日：2002-09-26
申请号：DE69807301
申请日：1998-09-18
Applicant: MICROCHIP TECH INC
Inventor： DRAKE RODNEY J , TRIECE JOSEPH W
Abstract: An instruction set for a microcontroller which has robust multiple word instructions. The instruction set has a plurality of instructions wherein the plurality of instructions comprises single word instructions and multiple word instructions. At least one bit is located in a predetermined location in all non-first words of all multiple word instructions. The bit will be decoded by the microcontroller as no operation bit if the first word of the multiple word instruction is not executed prior to execution of any succeeding words in the multiple word instruction.
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