公开(公告)号：ES2165651T3

公开(公告)日：2002-03-16

申请号：ES98119390

申请日：1998-10-14

Applicant: MICROCHIP TECH INC

Inventor： DRAKE RODNEY J ,  CHIAO JENNIFER ,  YACH RANDY L ,  WOJEWODA IGOR ,  TRIECE JOSEPH W ,  ALLEN STEVE

IPC: G06F9/32 ,  G06F9/34 ,  G06F9/38

Abstract: A system for allowing a two word instruction to be executed in a single cycle thereby allowing a processor system to increase memory space without reducing performance. A first address bus is coupled to the linearized program memory for sending addresses of instructions to be fetched to a linearized program memory. A pointer is coupled to the first address bus for storing an address location of a current instruction in the linearized program memory to be fetched and for placing the address location of the current instruction to be fetched on the first address bus. A second address bus is provided and has one end coupled to the output of the program memory and a second end coupled to the first address bus. The second address bus is used for placing an address of an operand of a second word of the two word instruction onto the first address bus after an address of an operand of a first word of the two word instruction has been placed on the first address bus. This allows the addresses of the first word and the second word to be combined to provide the full address value of the two word instruction in a single cycle.

公开(公告)号：DE69801355D1

公开(公告)日：2001-09-20

申请号：DE69801355

申请日：1998-10-14

Applicant: MICROCHIP TECH INC

Inventor： DRAKE J ,  CHIAO JENNIFER ,  YACH RANDY L ,  WOJEWODA IGOR ,  TRIECE JOSEPH W ,  ALLEN STEVE

IPC: G06F9/32 ,  G06F9/34 ,  G06F9/38

Abstract: A system for allowing a two word instruction to be executed in a single cycle thereby allowing a processor system to increase memory space without reducing performance. A first address bus is coupled to the linearized program memory for sending addresses of instructions to be fetched to a linearized program memory. A pointer is coupled to the first address bus for storing an address location of a current instruction in the linearized program memory to be fetched and for placing the address location of the current instruction to be fetched on the first address bus. A second address bus is provided and has one end coupled to the output of the program memory and a second end coupled to the first address bus. The second address bus is used for placing an address of an operand of a second word of the two word instruction onto the first address bus after an address of an operand of a first word of the two word instruction has been placed on the first address bus. This allows the addresses of the first word and the second word to be combined to provide the full address value of the two word instruction in a single cycle.

公开(公告)号：WO2008073883A3

公开(公告)日：2008-08-21

申请号：PCT/US2007086963

申请日：2007-12-10

Applicant: MICROCHIP TECH INC ,  SIMMONS MICHAEL ,  WOJEWODA IGOR

Inventor： SIMMONS MICHAEL ,  WOJEWODA IGOR

IPC: G06F9/445 ,  H03K3/037

CPC classification number: G06F1/3203 ,  G06F1/24

Abstract: A semiconductor integrated circuit device upon exiting from a low power mode, wakes up and re-initializes logic circuits so as to restore previous logic states of internal registers without disturbing input-output (I/O) configuration control and data states present at the time the low power mode was entered. Thus not distributing the operation of other devices connected to the semiconductor integrated circuit device previously in the low power mode. Once all internal logic and registers of the semiconductor integrated circuit device have been re-initialized, a "low power state wake-up and restore" signal may issue. This signal indicates that the I/O configuration control and data states stored in the I/O keeper cell at the time the integrated circuit device entered into the low power mode have been reinstated and control may be returned to the logic circuits and/or internal registers of the semiconductor integrated circuit device.

Abstract translation: 半导体集成电路器件在从低功率模式退出时唤醒并重新初始化逻辑电路，以恢复内部寄存器的先前逻辑状态而不干扰当时存在的输入 - 输出（I / O）配置控制和数据状态 进入低功耗模式。 因此，先前在低功率模式下不分配连接到半导体集成电路器件的其他器件的操作。 一旦半导体集成电路器件的所有内部逻辑和寄存器都被重新初始化，就会发出“低功耗状态唤醒和恢复”信号。 该信号指示在集成电路装置进入低功率模式时存储在I / O保持器单元中的I / O配置控制和数据状态已经恢复，并且控制可以返回到逻辑电路和/或内部 半导体集成电路器件的寄存器。

公开(公告)号：WO2006091468A3

公开(公告)日：2006-12-21

申请号：PCT/US2006005462

申请日：2006-02-16

Applicant: MICROCHIP TECH INC ,  MASGRAS CRISTIAN P ,  PYSKA MICHAEL ,  BOLES EDAWRD BRIAN ,  TRIECE JOSEPH W ,  WOJEWODA IGOR ,  CHEN MEI-LING

Inventor： MASGRAS CRISTIAN P ,  PYSKA MICHAEL ,  BOLES EDAWRD BRIAN ,  TRIECE JOSEPH W ,  WOJEWODA IGOR ,  CHEN MEI-LING

IPC: G06F11/27 ,  G11C29/46

CPC classification number: G01R31/31701 ,  G06F11/273 ,  G11C29/003 ,  G11C29/46

Abstract: A special mode key match comparison module has N-storage elements and a special mode key match comparator. The N-storage elements accumulate a serial data stream, and then determine whether a digital device should operate in a normal user mode, in a public programming mode, or in a particular private test mode. To reduce the possibility of accidentally decoding a false test or programming mode, the data stream has a sufficiently large number of N-bits to substantially reduce the probability of a false decode. To further reduce the possibility of accidentally decoding a programming or test mode, the special mode key match comparison module may be reset if less or more than N-clocks are detected during the accumulation of the N-bit serial data stream. The special mode key match data patterns may represent a normal user mode, a public programming mode, and particular private manufacturer test modes.

Abstract translation: 特殊模式键匹配比较模块具有N个存储元件和特殊模式键匹配比较器。 N个存储元件累积串行数据流，然后确定数字设备是否应以正常用户模式，公共编程模式或特定专用测试模式运行。 为了减少意外解码错误测试或编程模式的可能性，数据流具有足够大数目的N位以显着降低错误解码的可能性。 为了进一步降低意外解码编程或测试模式的可能性，如果在N位串行数据流的累积期间检测到少于或多于N个时钟，则可以重置特殊模式密钥匹配比较模块。 特殊模式键匹配数据模式可以表示正常用户模式，公共编程模式和特定的私人制造商测试模式。

公开(公告)号：DE112018004541T5

公开(公告)日：2020-05-28

申请号：DE112018004541

申请日：2018-10-12

Applicant: MICROCHIP TECH INC

Inventor： WOJEWODA IGOR ,  KRIS BRYAN ,  BOWLING STEPHEN ,  YUENYONGSGOOL YONG

IPC: H03K5/19

Abstract: Eine Taktüberwachung weist einen Testtakteingang als Referenztakteingang, einen weiteren Takteingang, eine Messschaltung und eine Steuerlogik auf. Die Messschaltung erzeugt eine Messung einer Frequenz oder eines Tastverhältnisses des Testtakteingangs unter Verwendung des Referenztakteingangs, die mit einem Schwellenwert verglichen wird. Die Steuerlogik bestimmt, ob die Messung den Schwellenwert überschritten hat und veranlasst auf der Grundlage der Messung, die den Schwellenwert überschritten hat, die Erzeugung einer weiteren Messung einer Frequenz oder eines Tastverhältnisses unter Verwendung des dritten Takteingangs in Kombination mit dem ersten Takteingang oder dem Referenztakteingang. Die Steuerlogik kann feststellen, ob die weitere Messung einen Schwellenwert überschritten hat, und kann basierend auf einer solchen Feststellung weiterhin feststellen, dass der Testtakteingang oder der Referenztakteingang fehlerhaft ist.

公开(公告)号：DE112018004320T5

公开(公告)日：2020-05-14

申请号：DE112018004320

申请日：2018-09-28

Applicant: MICROCHIP TECH INC

Inventor： KRIS BRYAN ,  WOJEWODA IGOR ,  BOWLING STEPHEN ,  YUENYONGSGOOL YONG

IPC: G04G3/04 ,  G06F1/08 ,  H03L1/02

Abstract: Eine temperaturkompensierende Taktfrequenzüberwachungsschaltung kann bereitgestellt werden, um eine Taktimpulsfrequenz in einer elektronischen Anordnung zu detektieren, die in Abhängigkeit von einer Betriebstemperatur der Anordnung einen fehlerhaften oder gefährlichen Betrieb der Anordnung verursachen kann. Die temperaturkompensierende Taktfrequenzüberwachungsschaltung weist einen Temperatursensor auf, der zum Messen einer Temperatur konfiguriert ist, die einer elektronischen Anordnung zugeordnet ist, einen Taktgeber, der eine Betriebsfrequenz aufweist, und ein Frequenzüberwachungssystem. Das Frequenzüberwachungssystem kann konfiguriert sein, um die Betriebsfrequenz des Taktgebers zu bestimmen, und zumindest basierend auf (a) der Betriebsfrequenz des Taktgebers und (b) der gemessenen Temperatur, die der elektronischen Anordnung zugeordnet ist, ein Korrekturmaßnahmesignal zu erzeugen, um eine Korrekturmaßnahme auszulösen, die der elektronischen Anordnung oder einer zugehörigen Anordnung zugeordnet ist. Das Temperatursensor-, Takt- und Frequenzüberwachungssystem kann beispielsweise in einem Mikrocontroller bereitgestellt werden.

公开(公告)号：DE69818434D1

公开(公告)日：2003-10-30

申请号：DE69818434

申请日：1998-11-27

Applicant: MICROCHIP TECH INC

Inventor： WOJEWODA IGOR ,  DRAKE RODNEY J ,  BOLES BRIAN E

IPC: G06F3/00 ,  G06F1/22 ,  G06F15/78 ,  H03K19/173 ,  G06F12/06

Abstract: The invention allows the programmer to designate one or more pins on a semiconductor device as either address pins, which are in addition to a predetermined set of address lines or as alternate I/O pins. The object of the invention is to provide the programmer with the capability of defining with preciseness the particular size of the address bus needed for a specific application. The invention is comprised of a programming port, optional programing logic, configuration logic, selection logic and a set of pins that may be configured as per the programmer's requirements. The invention is to exist on a single, monolithic semiconductor device.

公开(公告)号：AT250827T

公开(公告)日：2003-10-15

申请号：AT98122505

申请日：1998-11-27

Applicant: MICROCHIP TECH INC

Inventor： WOJEWODA IGOR ,  DRAKE RODNEY J ,  BOLES BRIAN E

IPC: G06F3/00 ,  G06F1/22 ,  G06F15/78 ,  H03K19/173 ,  G06F12/06

Abstract: The invention allows the programmer to designate one or more pins on a semiconductor device as either address pins, which are in addition to a predetermined set of address lines or as alternate I/O pins. The object of the invention is to provide the programmer with the capability of defining with preciseness the particular size of the address bus needed for a specific application. The invention is comprised of a programming port, optional programing logic, configuration logic, selection logic and a set of pins that may be configured as per the programmer's requirements. The invention is to exist on a single, monolithic semiconductor device.

公开(公告)号：DE69801355T2

公开(公告)日：2002-06-13

申请号：DE69801355

申请日：1998-10-14

Applicant: MICROCHIP TECH INC

Inventor： DRAKE J ,  CHIAO JENNIFER ,  YACH RANDY L ,  WOJEWODA IGOR ,  TRIECE JOSEPH W ,  ALLEN STEVE

IPC: G06F9/32 ,  G06F9/34 ,  G06F9/38

Abstract: A system for allowing a two word instruction to be executed in a single cycle thereby allowing a processor system to increase memory space without reducing performance. A first address bus is coupled to the linearized program memory for sending addresses of instructions to be fetched to a linearized program memory. A pointer is coupled to the first address bus for storing an address location of a current instruction in the linearized program memory to be fetched and for placing the address location of the current instruction to be fetched on the first address bus. A second address bus is provided and has one end coupled to the output of the program memory and a second end coupled to the first address bus. The second address bus is used for placing an address of an operand of a second word of the two word instruction onto the first address bus after an address of an operand of a first word of the two word instruction has been placed on the first address bus. This allows the addresses of the first word and the second word to be combined to provide the full address value of the two word instruction in a single cycle.

公开(公告)号：DE112019002278T5

公开(公告)日：2021-02-04

申请号：DE112019002278

申请日：2019-04-30

Applicant: MICROCHIP TECH INC

Inventor： BOWLING STEPHEN ,  WOJEWODA IGOR ,  BALU MANIVANNAN

IPC: G01R31/28 ,  G01R31/317

Abstract: Ein Halbleiterchip weist einen Rückkopplungspfad auf, der mit einem Ausgangspin gekoppelt ist, und eine Integritätsüberwachungsschaltung „IMC“. Der Ausgangspin ist kommunikativ mit einer Logikschaltung gekoppelt, die einen Datenwert erzeugt. Die IMC ist so ausgebildet, dass sie den Datenwert empfängt. Die IMC ist weiterhin so ausgebildet, dass sie einen gemessenen Datenwert von dem Ausgangspin empfängt, der durch den Rückkopplungspfad geleitet wird, den Datenwert und den gemessenen Datenwert vergleicht und basierend auf dem Vergleich bestimmt, ob ein Fehler aufgetreten ist.