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23 records (took 0.022 seconds)

    15.
    发明专利
    未知

    公开(公告)号：DE60130947D1

    公开(公告)日：2007-11-29

    申请号：DE60130947

    申请日：2001-08-16

    Applicant: ST MICROELECTRONICS SA

    Inventor： ARNAL VINCENT ,  TORRES JOAQUIM

    IPC: H01L21/02

    Abstract: The fabrication of a metal plate capacitor in the metallisation levels above an integrated circuit consists of depositing an insulating layer (11) of between 0.5 and 1.5 microns on the surface of an integrated circuit (10). Method then involves grooving the insulating layer to form slabs (12), depositing and smoothing a metallic material (14) to form conducting lines (L1, L2, L3, L4) in the slabs, locally drawing the insulating layer to eliminate all the gaps separating two conducting lines, depositing a dielectric layer (16) and depositing and engraving a second metallic material (17) to at least completely fill the inter-line gaps.

    16.
    发明专利
    未知

    公开(公告)号：FR2833106B1

    公开(公告)日：2005-02-25

    申请号：FR0115594

    申请日：2001-12-03

    Applicant: ST MICROELECTRONICS SA

    Inventor： FARCY ALEXIS ,  CORONEL PHILIPPE ,  ANCEY PASCAL ,  TORRES JOAQUIM

    IPC: B81B7/00 ,  B81C3/00 ,  H01L21/50 ,  H01L21/56 ,  B81C1/00

    Abstract: The circuit includes a first semiconductor substrate supporting the electronic circuit, and a second substrate carrying an electromechanical component. The two substrates are glued together forming a sealed and protective enclosure for the auxiliary component. The first phase of manufacture includes forming the semiconductor chip (PC) within a first substrate, and forming a cavity in the upper surface of this substrate to accommodate an auxiliary component. A wall remains around the cavity, leaving the cavity as a well. The second phase includes formation of the auxiliary component (CAX) on a second semiconductor substrate (SB2), separate from the first. The second substrate is then turned over and applied to the first substrate as a lid with the auxiliary component hanging within the cavity of the first substrate. The two substrates are glued together forming a sealed and protective enclosure for the auxiliary component.

    17.
    发明专利
    未知

    公开(公告)号：FR2813142B1

    公开(公告)日：2002-11-29

    申请号：FR0010697

    申请日：2000-08-17

    Applicant: ST MICROELECTRONICS SA

    Inventor： AMAL VINCENT ,  TORRES JOAQUIM

    IPC: H01L21/02 ,  H01G4/33 ,  H01L21/71

    Abstract: The fabrication of a metal plate capacitor in the metallisation levels above an integrated circuit consists of depositing an insulating layer (11) of between 0.5 and 1.5 microns on the surface of an integrated circuit (10). Method then involves grooving the insulating layer to form slabs (12), depositing and smoothing a metallic material (14) to form conducting lines (L1, L2, L3, L4) in the slabs, locally drawing the insulating layer to eliminate all the gaps separating two conducting lines, depositing a dielectric layer (16) and depositing and engraving a second metallic material (17) to at least completely fill the inter-line gaps.

    19.
    发明专利
    未知

    公开(公告)号：FR2813142A1

    公开(公告)日：2002-02-22

    申请号：FR0010697

    申请日：2000-08-17

    Applicant: ST MICROELECTRONICS SA

    Inventor： AMAL VINCENT ,  TORRES JOAQUIM

    IPC: H01L21/02 ,  H01G4/33 ,  H01L21/71

    Abstract: The fabrication of a metal plate capacitor in the metallisation levels above an integrated circuit consists of depositing an insulating layer (11) of between 0.5 and 1.5 microns on the surface of an integrated circuit (10). Method then involves grooving the insulating layer to form slabs (12), depositing and smoothing a metallic material (14) to form conducting lines (L1, L2, L3, L4) in the slabs, locally drawing the insulating layer to eliminate all the gaps separating two conducting lines, depositing a dielectric layer (16) and depositing and engraving a second metallic material (17) to at least completely fill the inter-line gaps.

    Method for implementing insulated metallic interconnections in integrated circuits
    20.
    发明专利
    Method for implementing insulated metallic interconnections in integrated circuits 未知

    公开(公告)号：FR2803093A1

    公开(公告)日：2001-06-29

    申请号：FR9916489

    申请日：1999-12-24

    Applicant: ST MICROELECTRONICS SA

    Inventor： GAYET PHILIPPE ,  TORRES JOAQUIM ,  HAOND MICHEL

    IPC: H01L21/768 ,  H01L21/28 ,  H01L23/528

    Abstract: The method for the formation of a metallization level in an integrated circuit comprises the following steps: the formaton of metallic zones (11-14) of that level separated laterally by a first insulator layer (6), the elimination of first insulator layer, and the deposition of a second insulator layer (24) in a nonuniform fashion to have cavities (26) formed between neighbouring metallic zones. The elimination of the first insulator layer is done through a mask in a manner to leave in place the portions (22) of the first insulator layer outside the regions where the metallic zones are close to one another. The feedthroughs or vias in layers (2,3) and (6,24) are filled with metal (4,30), and guard zones (21) ensure that there is no spreading of metal to neighbouring cavities. The semiconductor structure can contain two levels of metallization, and the cavities at two levels can be connected in pairs. In a variant of the method, a porous material as eg. aerogel or xerogel is deposited in a thickness sufficient to fill in all space between metallic zones (11-14) and slightly to overflow, which is covered by an insulator layer of standard structure. In another variant of the method, the mask is discontinuous and has substantially the same step as that of closely spaced metallic zones.

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