公开(公告)号：FR2773264B1

公开(公告)日：2001-06-08

申请号：FR9716654

申请日：1997-12-30

Applicant: ST MICROELECTRONICS SA

Inventor： GAYET PHILIPPE ,  BRUNEL CHANTAL ,  MARTIN STEPHANE

IPC: H01L21/3205 ,  G01R31/28 ,  G03F7/20 ,  H01L23/52 ,  H01L23/528

公开(公告)号：FR2787240B1

公开(公告)日：2002-08-09

申请号：FR9815769

申请日：1998-12-14

Applicant: ST MICROELECTRONICS SA

Inventor： SCHOELLKOPF JEAN PIERRE ,  GAYET PHILIPPE

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/4763 ,  H01L21/8239

Abstract: Four transistors is formed in a semiconductor substrate and interconnected by a local interconnection layer (M0) situated under a first metallisation level (M1). Two resistances (LIL1,LIL2) provides local interconnection layer between the metallisation layer (M0) and the first metallisation level (M1). An Independent claim is included for: (a) a method of formation of integrated circuit disposed on two levels of metallisation

公开(公告)号：FR2789803B1

公开(公告)日：2002-03-08

申请号：FR9901741

申请日：1999-02-12

Applicant: ST MICROELECTRONICS SA

Inventor： FROMENT BENOIT ,  GAYET PHILIPPE ,  VAN DER VEGT ERIK

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532

Abstract: At least one layer of a dielectric material 3 is deposited on a copper track 1 covered with an encapsulation layer 2. A cavity 6 is etched in the layer of dielectric material at the location of the future vertical connection. At least one protective layer is deposited in said cavity to preclude diffusion of copper 7. The protective layer 7 at the bottom of the cavity 6 is subjected to an anisotropic etching treatment and also the encapsulation layer 2 is subjected to etching, whereafter the cavity is filled with copper. The copper particles pulverized during etching the encapsulation layer do not contaminate the dielectric material 3.

公开(公告)号：FR2803093A1

公开(公告)日：2001-06-29

申请号：FR9916489

申请日：1999-12-24

Applicant: ST MICROELECTRONICS SA

Inventor： GAYET PHILIPPE ,  TORRES JOAQUIM ,  HAOND MICHEL

IPC: H01L21/768 ,  H01L21/28 ,  H01L23/528

Abstract: The method for the formation of a metallization level in an integrated circuit comprises the following steps: the formaton of metallic zones (11-14) of that level separated laterally by a first insulator layer (6), the elimination of first insulator layer, and the deposition of a second insulator layer (24) in a nonuniform fashion to have cavities (26) formed between neighbouring metallic zones. The elimination of the first insulator layer is done through a mask in a manner to leave in place the portions (22) of the first insulator layer outside the regions where the metallic zones are close to one another. The feedthroughs or vias in layers (2,3) and (6,24) are filled with metal (4,30), and guard zones (21) ensure that there is no spreading of metal to neighbouring cavities. The semiconductor structure can contain two levels of metallization, and the cavities at two levels can be connected in pairs. In a variant of the method, a porous material as eg. aerogel or xerogel is deposited in a thickness sufficient to fill in all space between metallic zones (11-14) and slightly to overflow, which is covered by an insulator layer of standard structure. In another variant of the method, the mask is discontinuous and has substantially the same step as that of closely spaced metallic zones.

公开(公告)号：FR2782838A1

公开(公告)日：2000-03-03

申请号：FR9810691

申请日：1998-08-25

Applicant: ST MICROELECTRONICS SA

Inventor： GAYET PHILIPPE ,  LALANNE FREDERIC

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/28 ,  H01L23/528

Abstract: IC manufacture, comprises a self-aligned double damascene process in which a stop layer is provided only at the locations of overlying metallization level lines. IC manufacturing process comprises: (a) depositing a stop layer on a dielectric layer covering a metallization level 'n', the stop layer being selectively etchable with respect to the dielectric layer; (b) etching trenches in the stop layer; (c) depositing a second dielectric layer; (d) forming trenches in the second dielectric layer for the 'n + 1' level lines and holes in the first dielectric layer for the 'n' level vias; and (e) filling the trenches and holes with metal. During trench etching in the stop layer, the stop layer is etched in zones not corresponding to the lines of the 'n + 1' metallization level, so as to leave the stop layer only in these zones, with the exception of the zones corresponding to the 'n' level vias. An Independent claim is also included for an IC manufactured by the above process. Preferred Features: The stop layer is formed of tantalum, titanium or their nitrides.

公开(公告)号：FR2773264A1

公开(公告)日：1999-07-02

申请号：FR9716654

申请日：1997-12-30

Applicant: ST MICROELECTRONICS SA

Inventor： GAYET PHILIPPE ,  BRUNEL CHANTAL ,  MARTIN STEPHANE

IPC: H01L21/3205 ,  G01R31/28 ,  G03F7/20 ,  H01L23/52 ,  H01L23/528

Abstract: When photolithography causes track offsets, the two metallization layers attachments are changed by the same resistance.

公开(公告)号：FR2789803A1

公开(公告)日：2000-08-18

申请号：FR9901741

申请日：1999-02-12

Applicant: ST MICROELECTRONICS SA

Inventor： FROMENT BENOIT ,  GAYET PHILIPPE ,  VAN DER VEGT ERIK

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532

Abstract: At least one layer of a dielectric material (3) is deposited on a copper track (1) covered with an encapsulation layer (2). A cavity (6) is etched in the layer of dielectric material at the location of the future vertical connection. At least one protective layer (7) is deposited in said cavity to preclude diffusion of copper. The protective layer (7) at the bottom of the cavity (6) is subjected to an anisotropic etching treatment and also the encapsulation layer (2) is subjected to etching, whereafter the cavity is filled with copper. The copper particles pulverized during etching of the encapsulation layer do not contaminate the dielectric material.

公开(公告)号：FR2786609A1

公开(公告)日：2000-06-02

申请号：FR9814908

申请日：1998-11-26

Applicant: ST MICROELECTRONICS SA

Inventor： GAYET PHILIPPE

IPC: H01L21/768 ,  H01L21/82 ,  H01L21/822 ,  H01L23/522 ,  H01L27/04 ,  H01L23/528 ,  H01L21/3213

Abstract: The integrated circuit has tracks of at least one metallization layer provided with dielectric layers and metallized vias connecting the tracks of two neighboring layers. At least a part of at least one metallization layer n is divided up into two partial layers offset in height. At least one via (12) connects the track of an upper partial layer and an element located under the dielectric layer of layer n. The via (12) passes through the dielectric layer of the level n and the dielectric material separating the tracks of the lower partial layer. At least one via (13) connects a track of the lower partial layer and a track of a metallization layer n+1. The via (13) passes through the dielectric layer of level n+1 and the dielectric material separating the tracks of the upper partial layer. At least one via connects a track of the lower partial layer and an element located below the dielectric material of level n. The tracks of the part of the metallization layer are distributed between a partial upper level n2 and a partial; lower level n1, and they do not cross each other. The upper and lower partial layers are adjacent and are separated by a supplementary dielectric material layer. An Independent claim is given for a method of manufacturing the integrated circuit.

公开(公告)号：FR2803092B1

公开(公告)日：2002-11-29

申请号：FR9916488

申请日：1999-12-24

Applicant: ST MICROELECTRONICS SA

Inventor： TORRES JOAQUIM ,  GAYET PHILIPPE ,  HAOND MICHEL

IPC: H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L21/28 ,  H01L23/528

Abstract: One embodiment of the invention is directed to a method of forming a metallization level of an integrated circuit including the steps of forming metal areas of a metallization level laterally separated by a first insulating layer, removing the first insulating layer, non-conformally depositing a second insulating layer so that gaps can form between neighboring metal areas, or to obtain a porous layer. The removal of the first insulating layer is performed through a mask, to leave in place guard areas of the first insulating layer around the portions of the metal areas intended for being contacted by a via crossing the second insulating layer.

公开(公告)号：DE69611632D1

公开(公告)日：2001-03-01

申请号：DE69611632

申请日：1996-05-15

Applicant: ST MICROELECTRONICS SA

Inventor： GAYET PHILIPPE

IPC: H01L21/316 ,  H01L21/76 ,  H01L21/762

Abstract: The invention provides a method for producing an isolation region on a surface of a semiconductor substrate comprising the steps of: forming and patterning a masking layer; forming an isolating layer so that a notch exists between an edge of the masking layer and the upper surface of the isolating layer; forming a filling layer over the masking layer and the isolating layer, so that it completely fills the notch; forming field protection spacers adjacent to the masking layer; partially removing the filling layer to expose the upper surface of the isolation layer, the notch remaining filled with a part of the filling layer; and partially removing the isolating layer from its upper limit until this upper limit is substantially coplanar with the upper surface of the semiconductor substrate.