公开(公告)号：FR2848339B1

公开(公告)日：2005-08-26

申请号：FR0215370

申请日：2002-12-05

Applicant: ST MICROELECTRONICS SA

Inventor： BOUCHE GUILLAUME ,  ANCEY PASCAL ,  FROMENT BENOIT

IPC: B81B7/00 ,  H01S5/022 ,  H01L23/31 ,  B81C3/00

Abstract: The adhesion of a first element (1), of which at least a part of the surface is coated with silicon, on a second element (2), of which at least a part of the surface is coated with nickel, incorporates an adhesion stage effected by NiSi welding at greater than 250degreesC, the rugosity between the two parts of the surface of the two elements being less than 1 micron. An Independent claim is also included for an integrated circuit incorporating two elements joined by NiSi welding.

公开(公告)号：FR2789803B1

公开(公告)日：2002-03-08

申请号：FR9901741

申请日：1999-02-12

Applicant: ST MICROELECTRONICS SA

Inventor： FROMENT BENOIT ,  GAYET PHILIPPE ,  VAN DER VEGT ERIK

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532

Abstract: At least one layer of a dielectric material 3 is deposited on a copper track 1 covered with an encapsulation layer 2. A cavity 6 is etched in the layer of dielectric material at the location of the future vertical connection. At least one protective layer is deposited in said cavity to preclude diffusion of copper 7. The protective layer 7 at the bottom of the cavity 6 is subjected to an anisotropic etching treatment and also the encapsulation layer 2 is subjected to etching, whereafter the cavity is filled with copper. The copper particles pulverized during etching the encapsulation layer do not contaminate the dielectric material 3.

公开(公告)号：FR2780162B1

公开(公告)日：2000-09-08

申请号：FR9807788

申请日：1998-06-19

Applicant: ST MICROELECTRONICS SA

Inventor： FROMENT BENOIT

IPC: G01R27/26 ,  G01R31/28 ,  G01R27/16

公开(公告)号：DE60045501D1

公开(公告)日：2011-02-24

申请号：DE60045501

申请日：2000-02-04

Applicant: NXP BV ,  ST MICROELECTRONICS SA

Inventor： FROMENT BENOIT ,  GAYET PHILLIPE ,  VAN DER VEGT ERIK

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/285 ,  H01L21/3205 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532

公开(公告)号：FR2856843A1

公开(公告)日：2004-12-31

申请号：FR0307690

申请日：2003-06-25

Applicant: ST MICROELECTRONICS SA

Inventor： FROMENT BENOIT ,  WACQUANT FRANCOIS

IPC: H01L21/285 ,  H01L21/56 ,  H01L23/29

Abstract: Protection of a semiconductor material against the formation of a metal silicide comprises the formation, on the material, of a layer of silicon-germanium alloy using the following stages: (a) deposition of the layer of silicon-germanium alloy (10) on the integrated circuit assembly; (b) removal of this layer in the zones needed for the formation of a silicide; (c) deposition of a metal on the structure obtained by the removal; (d) formation of the metal silicide (110) on the defined zones; (e) removal of the metal which has not reacted and of the ternary metal-silicon-germanium alloy possibly formed; (f) removal of the layer of silicon-germanium alloy in order to expose the non silicide component.

公开(公告)号：FR2848339A1

公开(公告)日：2004-06-11

申请号：FR0215370

申请日：2002-12-05

Applicant: ST MICROELECTRONICS SA

Inventor： BOUCHE GUILLAUME ,  ANCEY PASCAL ,  FROMENT BENOIT

IPC: B81B7/00 ,  H01S5/022 ,  H01L23/31 ,  B81C3/00

Abstract: The adhesion of a first element (1), of which at least a part of the surface is coated with silicon, on a second element (2), of which at least a part of the surface is coated with nickel, incorporates an adhesion stage effected by NiSi welding at greater than 250degreesC, the rugosity between the two parts of the surface of the two elements being less than 1 micron. An Independent claim is also included for an integrated circuit incorporating two elements joined by NiSi welding.

公开(公告)号：DE60107147T2

公开(公告)日：2005-10-27

申请号：DE60107147

申请日：2001-05-31

Applicant: ST MICROELECTRONICS SA

Inventor： BIANCHI RAUL ANDES ,  FROMENT BENOIT

IPC: H03M1/10 ,  H03M1/78 ,  H03M1/42

Abstract: The control device (DCA) comprises a capacitive structure (SCA) having an input node (ND0) and n output nodes (ND1, ..., NDn), where n is greater or equal to 2, then r integrated capacitors (C) connected in series between neighbouring nodes, where r is greater or equal to 1, eg. r=1, an integrated capacitor (C) connected between the input node and the ground, and between the n-th node of output and the ground, r capacitive branches connected in parallel between the ground and each node, including the first node of output and the (n-1)th node of output, where each branch BRi (i=1, ..., n-1) comprises r+1, eg. 2, integrated capacitors (C) connected in series, and all capacitors (C) are theoretically identical. The device also comprises the charging means (MCH) including a reference voltage source (STR) and a controlled switch (Sv), the measuring means including an ammeter (Amp) and a controlled switch (Si), and the comparison means for comparing each measured value of nodal charge to the theoretical value of nodal charge with taking into account a predetermined tolerance. The device also comprises, for each node of capacitive structure (SCA), a controlled switch (Sres) for discharge, connected between the node and the ground. The device is utilized for the control of integrated capacitors belonging to an integrated circuit (IC) situated in a zone of a semiconductor wafer and demarcated by cutting lines, where the capacitive structure is inserted in the cutting lines, and the surface of frame of capacitors of capacitive structure is at most equal to the minimum surface of frame of capacitors of integrated circuit. The method of control includes the following steps: the discharge of all nodes; the charging of all nodes; the connection of ammeter between the measured node and the ground; and the disconnection of ammeter.

公开(公告)号：DE60107147D1

公开(公告)日：2004-12-23

申请号：DE60107147

申请日：2001-05-31

Applicant: ST MICROELECTRONICS SA

Inventor： BIANCHI RAUL ANDES ,  FROMENT BENOIT

IPC: H03M1/10 ,  H03M1/78

Abstract: The control device (DCA) comprises a capacitive structure (SCA) having an input node (ND0) and n output nodes (ND1, ..., NDn), where n is greater or equal to 2, then r integrated capacitors (C) connected in series between neighbouring nodes, where r is greater or equal to 1, eg. r=1, an integrated capacitor (C) connected between the input node and the ground, and between the n-th node of output and the ground, r capacitive branches connected in parallel between the ground and each node, including the first node of output and the (n-1)th node of output, where each branch BRi (i=1, ..., n-1) comprises r+1, eg. 2, integrated capacitors (C) connected in series, and all capacitors (C) are theoretically identical. The device also comprises the charging means (MCH) including a reference voltage source (STR) and a controlled switch (Sv), the measuring means including an ammeter (Amp) and a controlled switch (Si), and the comparison means for comparing each measured value of nodal charge to the theoretical value of nodal charge with taking into account a predetermined tolerance. The device also comprises, for each node of capacitive structure (SCA), a controlled switch (Sres) for discharge, connected between the node and the ground. The device is utilized for the control of integrated capacitors belonging to an integrated circuit (IC) situated in a zone of a semiconductor wafer and demarcated by cutting lines, where the capacitive structure is inserted in the cutting lines, and the surface of frame of capacitors of capacitive structure is at most equal to the minimum surface of frame of capacitors of integrated circuit. The method of control includes the following steps: the discharge of all nodes; the charging of all nodes; the connection of ammeter between the measured node and the ground; and the disconnection of ammeter.

公开(公告)号：FR2809887B1

公开(公告)日：2002-08-23

申请号：FR0007227

申请日：2000-06-06

Applicant: ST MICROELECTRONICS SA

Inventor： BIANCHI RAUL ANDREAS ,  FROMENT BENOIT

IPC: H03M1/10 ,  H03M1/78 ,  H03M1/06

Abstract: The control device (DCA) comprises a capacitive structure (SCA) having an input node (ND0) and n output nodes (ND1, ..., NDn), where n is greater or equal to 2, then r integrated capacitors (C) connected in series between neighbouring nodes, where r is greater or equal to 1, eg. r=1, an integrated capacitor (C) connected between the input node and the ground, and between the n-th node of output and the ground, r capacitive branches connected in parallel between the ground and each node, including the first node of output and the (n-1)th node of output, where each branch BRi (i=1, ..., n-1) comprises r+1, eg. 2, integrated capacitors (C) connected in series, and all capacitors (C) are theoretically identical. The device also comprises the charging means (MCH) including a reference voltage source (STR) and a controlled switch (Sv), the measuring means including an ammeter (Amp) and a controlled switch (Si), and the comparison means for comparing each measured value of nodal charge to the theoretical value of nodal charge with taking into account a predetermined tolerance. The device also comprises, for each node of capacitive structure (SCA), a controlled switch (Sres) for discharge, connected between the node and the ground. The device is utilized for the control of integrated capacitors belonging to an integrated circuit (IC) situated in a zone of a semiconductor wafer and demarcated by cutting lines, where the capacitive structure is inserted in the cutting lines, and the surface of frame of capacitors of capacitive structure is at most equal to the minimum surface of frame of capacitors of integrated circuit. The method of control includes the following steps: the discharge of all nodes; the charging of all nodes; the connection of ammeter between the measured node and the ground; and the disconnection of ammeter.

公开(公告)号：FR2809887A1

公开(公告)日：2001-12-07

申请号：FR0007227

申请日：2000-06-06

Applicant: ST MICROELECTRONICS SA

Inventor： BIANCHI RAUL ANDREAS ,  FROMENT BENOIT

IPC: H03M1/10 ,  H03M1/78 ,  H03M1/06

Abstract: The control device (DCA) comprises a capacitive structure (SCA) having an input node (ND0) and n output nodes (ND1, ..., NDn), where n is greater or equal to 2, then r integrated capacitors (C) connected in series between neighbouring nodes, where r is greater or equal to 1, eg. r=1, an integrated capacitor (C) connected between the input node and the ground, and between the n-th node of output and the ground, r capacitive branches connected in parallel between the ground and each node, including the first node of output and the (n-1)th node of output, where each branch BRi (i=1, ..., n-1) comprises r+1, eg. 2, integrated capacitors (C) connected in series, and all capacitors (C) are theoretically identical. The device also comprises the charging means (MCH) including a reference voltage source (STR) and a controlled switch (Sv), the measuring means including an ammeter (Amp) and a controlled switch (Si), and the comparison means for comparing each measured value of nodal charge to the theoretical value of nodal charge with taking into account a predetermined tolerance. The device also comprises, for each node of capacitive structure (SCA), a controlled switch (Sres) for discharge, connected between the node and the ground. The device is utilized for the control of integrated capacitors belonging to an integrated circuit (IC) situated in a zone of a semiconductor wafer and demarcated by cutting lines, where the capacitive structure is inserted in the cutting lines, and the surface of frame of capacitors of capacitive structure is at most equal to the minimum surface of frame of capacitors of integrated circuit. The method of control includes the following steps: the discharge of all nodes; the charging of all nodes; the connection of ammeter between the measured node and the ground; and the disconnection of ammeter.