公开(公告)号：DE69325278D1

公开(公告)日：1999-07-15

申请号：DE69325278

申请日：1993-12-31

Applicant: ST MICROELECTRONICS SRL

Inventor： CASAGRANDE GIULIO ,  CAMERLENGHI EMILIO

IPC: G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30

Abstract: A voltage regulator for electrically programmable non-volatile semiconductor memory devices of the type comprising a gain stage (3), supplied by a programming voltage (Vpp) and having an input terminal connected to a divider (6) of said programming voltage (Vpp) and an output terminal (U) connected to a programming line (5) of at least one memory cell (2) comprises at least one circuit element (4) capable of adapting the line programming voltage (5) to the length (L) of the memory cell (2). This solution makes it possible to have on the bit line of the memory device a drain voltage varying according to the actual length of the memory cell.

公开(公告)号：DE60205389D1

公开(公告)日：2005-09-08

申请号：DE60205389

申请日：2002-11-28

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMERLENGHI EMILIO ,  CAMPARDO GIOVANNI ,  GHILARDI TECLA

IPC: G11C16/34

公开(公告)号：DE69426818T2

公开(公告)日：2001-10-18

申请号：DE69426818

申请日：1994-06-10

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  CAMERLENGHI EMILIO

IPC: G11C17/00 ,  G11C16/06 ,  G11C16/34 ,  G11C29/00 ,  G11C29/04 ,  G11C29/12 ,  G11C29/50 ,  H01L27/00 ,  G06F11/20

Abstract: Since fault phenomena such as lowering of the cell gain and cell emptying occur during normal operation the present invention proposes that in the memory device the row and/or column address decoding means (RDEC,CDEC) comprise at least one non-volatile memory (NVM) for address mapping and that the reading and writing control logic (CL) comprise means (TST) designed to identify cell faults in the rows and/or columns of the matrix (MAT) of the memory device and writing means (WM) designed to write on said non-volatile memory (NVM) during normal operation addresses corresponding to redundant rows and/or columns (RID) present in the matrix (MAT) to rectify said faults.

公开(公告)号：IT1304059B1

公开(公告)日：2001-03-07

申请号：ITMI982843

申请日：1998-12-29

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMERLENGHI EMILIO ,  COLABELLA ELIO

IPC: H01L21/8247 ,  H01L27/105

公开(公告)号：DE69325714D1

公开(公告)日：1999-08-26

申请号：DE69325714

申请日：1993-12-31

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMERLENGHI EMILIO ,  CASAGRANDE GIULIO

IPC: G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30

Abstract: A voltage regulator for electrically programmable non-volatile semiconductor memory devices of the type comprising a gain stage (3), supplied by a programming voltage (Vpp) and having an input terminal connected to a divider (6) of said programming voltage (Vpp) and an output terminal (U) connected to a programming line (5) of at least one memory cell (2) comprises at least one circuit element (4) capable of adapting the line programming voltage (5) to the length (L) of the memory cell (2). This solution makes it possible to have on the bit line of the memory device a drain voltage varying according to the actual length of the memory cell.

公开(公告)号：DE69942862D1

公开(公告)日：2010-11-25

申请号：DE69942862

申请日：1999-12-06

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMERLENGHI EMILIO

IPC: H01L21/8239 ,  H01L21/8247 ,  H01L27/105

公开(公告)号：DE69637095D1

公开(公告)日：2007-07-05

申请号：DE69637095

申请日：1996-12-24

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMERLENGHI EMILIO ,  COLABELLA ELIO ,  PIVIDORI LUCA ,  REBORA ADRIANA SGS-THOMSON

IPC: H01L21/8247 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/768 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: Self-aligned etching process for providing a plurality of mutually parallel word lines in a first conducting layer (11,12) deposited over a planarized architecture (9) obtained starting from a semiconductor substrate (1) on which is provided a plurality of active elements extending along separate parallel lines e.g. memory cell bit lines (13) and comprising gate regions made up of a first conducting layer (4), an intermediate dielectric layer (5) and a second conducting layer (6) with said regions being insulated from each other by insulation regions (7,8) to form said architecture (9) with said word lines being defined photolithographically by protective strips implemented by means of: a vertical profile etching for complete removal from the unprotected areas of the first conducting layer (11,12), of the second conducting layer (6) and of the intermediate dielectric layer (5) respectively, and a following isotropic etching of the first conducting layer (4).

公开(公告)号：DE69636738D1

公开(公告)日：2007-01-11

申请号：DE69636738

申请日：1996-12-27

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMERLENGHI EMILIO ,  CAPRARA PAOLO ,  FONTANA GABRIELLA

IPC: H01L21/28 ,  H01L27/00 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: The present invention relates to a process for creation of contacts (25) in semiconductor electronic devices and in particular on bit lines of non-volatile memories with cross-point structure comprising memory cell matrices in which the bit lines are parallel unbroken diffusion strips (12) extending along a column of the matrix with the contacts (25) being provided through associated contact apertures (24) defined through a dielectric layer (21) deposited over a contact region defined on a semiconductor substrate (11) at one end of the bit lines (12). The process calls for a step of implantation and following diffusion of contact areas (22) provided in the substrate (11) at opposite sides of each bit line (12) to be contacted to widen the area designed to receive the contacts (25).

公开(公告)号：IT1318145B1

公开(公告)日：2003-07-23

申请号：ITMI20001567

申请日：2000-07-11

Applicant: ST MICROELECTRONICS SRL

Inventor： BEZ ROBERTO ,  CAMERLENGHI EMILIO ,  RATTI STEFANO

IPC: H01L21/8247 ,  H01L27/115

Abstract: A process for fabricating non-volatile memory cells on a semiconductor substrate comprises the following steps: forming a stack structure comprised of a first polysilicon layer (3) isolated from the substrate by an oxide layer (2); cascade etching the first polysilicon layer (3), oxide layer (2), and semiconductor substrate (1) to define a first portion of a floating gate region of the cell and at least one trench (6) bordering an active area (AA) of the memory cell; filling the at least one trench (6) with an isolation layer (7); depositing a second polysilicon layer (8) onto the whole exposed surface of the semiconductor; and etching away the second polysilicon layer (8) to expose the floating gate region formed in the first polysilicon layer (3), thereby forming extensions (9) adjacent to the above portion of the first polysilicon layer (3).

公开(公告)号：ITMI20001567A1

公开(公告)日：2002-01-11

申请号：ITMI20001567

申请日：2000-07-11

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMERLENGHI EMILIO ,  BEZ ROBERTO ,  RATTI STEFANO

IPC: H01L21/8247 ,  H01L27/115

Abstract: A process for fabricating non-volatile memory cells on a semiconductor substrate comprises the following steps: forming a stack structure comprised of a first polysilicon layer (3) isolated from the substrate by an oxide layer (2); cascade etching the first polysilicon layer (3), oxide layer (2), and semiconductor substrate (1) to define a first portion of a floating gate region of the cell and at least one trench (6) bordering an active area (AA) of the memory cell; filling the at least one trench (6) with an isolation layer (7); depositing a second polysilicon layer (8) onto the whole exposed surface of the semiconductor; and etching away the second polysilicon layer (8) to expose the floating gate region formed in the first polysilicon layer (3), thereby forming extensions (9) adjacent to the above portion of the first polysilicon layer (3).