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    11.
    发明专利
    未知

    公开(公告)号：ITMI20000687A1

    公开(公告)日：2001-10-01

    申请号：ITMI20000687

    申请日：2000-03-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： COMMODARO STEFANO ,  CAMPARDO GIOVANNI ,  PICCA MASSIMILIANO ,  MONGELLI PATRIZIA

    IPC: G11C29/56

    Abstract: A method and control device is used for testing electronic memory devices. The method comprises loading test data and/or instructions into a control logic circuit portion associated with a matrix array of memory cells and integrated storage circuitry. According to the invention, a test operation control device is used temporarily instead of the control logic, the test operation control device being external of and connected detachably to the memory device. Advantageously, the test operation control device is a matrix cell array external of the memory.

    13.
    发明专利
    未知

    公开(公告)号：ITTO20010529D0

    公开(公告)日：2001-06-01

    申请号：ITTO20010529

    申请日：2001-06-01

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  ZANARDI STEFANO ,  PICCA MASSIMILIANO ,  RAVASIO ROBERTO

    IPC: G06F11/10 ,  G06F12/00

    Abstract: A method for error control in multilevel memory cells storing a configurable number of bits. The error control is performed using an error-control code which operates, in the encoding phase, on b-bit binary strings made up of k symbols of r-bit data. When the memory cells store a number r of bits, a data symbol is formed only with the data bits stored in a memory cell. When the memory cells store a number s of bits smaller than r, a data symbol is formed with the data bits stored in a memory cell and with r-s bits having a pre-determined logic value, in which the data bits stored in the memory cell are arranged in the least significant part of the data symbol, and the r-s bits having a pre-determined logic value are arranged in the most significant part of the data symbol.

    14.
    发明专利
    未知

    公开(公告)号：ITMI20000687D0

    公开(公告)日：2000-03-31

    申请号：ITMI20000687

    申请日：2000-03-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： COMMODARO STEFANO ,  CAMPARDO GIOVANNI ,  PICCA MASSIMILIANO ,  MONGELLI PATRIZIA

    IPC: G11C29/56

    Abstract: A method and control device is used for testing electronic memory devices. The method comprises loading test data and/or instructions into a control logic circuit portion associated with a matrix array of memory cells and integrated storage circuitry. According to the invention, a test operation control device is used temporarily instead of the control logic, the test operation control device being external of and connected detachably to the memory device. Advantageously, the test operation control device is a matrix cell array external of the memory.

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