公开(公告)号：ITMI20000832A1

公开(公告)日：2001-10-15

申请号：ITMI20000832

申请日：2000-04-13

Applicant: ST MICROELECTRONICS SRL

Inventor： GUAITINI GIOVANNI ,  ROLANDI PIER LUIGI ,  ROCCHI ALESSANDRO ,  BISIO MARCO ,  DE SANDRE GUIDO ,  PASOTTI MARCO

IPC: G01R31/28

Abstract: A digital device for testing and calibrating the oscillation frequency of an integrated oscillator circuit, the testing and calibrating device has as input at least first and second control parameters corresponding to limiting values of a predetermined range of values of the oscillation frequency sought for the integrated oscillator circuit, and it includes a comparison circuit for comparing a signal of known duration and a signal from the integrated oscillator circuit; a circuit connected to the comparison circuit, for generating calibration values for the signal from the integrated oscillator circuit; and a circuit for forcing storage of final calibration values of the signal from the integrated oscillator circuit into a storage and control section of the integrated oscillator circuit.

公开(公告)号：ITTO980961A1

公开(公告)日：2000-05-15

申请号：ITTO980961

申请日：1998-11-13

Applicant: ST MICROELECTRONICS SRL

Inventor： CANEGALLO ROBERTO ,  PASOTTI MARCO ,  ROLANDI PIER LUIGI ,  GUAITINI GIOVANNI

IPC: G11C16/12

Abstract: The device comprises a current mirror circuit having a first and a second node connected, respectively, to a constant current source and to a drain terminal of a memory cell to be programmed. A voltage generating circuit is connected to the first node to bias it at a constant reference voltage (VR); an operational amplifier has an inverting input connected to the first node, a non-inverting input connected to the second node, and an output connected to the control terminal of the memory cell. Thereby, the drain terminal of the memory cell is biased at the constant reference voltage, having a value sufficient for programming, and the operational amplifier and the memory cell form a negative feedback loop that supplies, on the control terminal of the memory cell, a ramp voltage (VPCX) that causes writing of the memory cell. The ramp voltage increases with the same speed as the threshold voltage and can thus be used to know when the desired threshold value is reached, and thus when programming must be stopped. The presence of a bias transistor between the second node and the memory cell enables use of the same circuit also during reading.

公开(公告)号：ITTO980906A1

公开(公告)日：2000-04-26

申请号：ITTO980906

申请日：1998-10-23

Applicant: ST MICROELECTRONICS SRL

Inventor： CANEGALLO ROBERTO ,  PASOTTI MARCO ,  ROLANDI PIER LUIGI ,  GUAITINI GIOVANNI

IPC: G11C20060101

公开(公告)号：ITTO991098D0

公开(公告)日：1999-12-14

申请号：ITTO991098

申请日：1999-12-14

Applicant: ST MICROELECTRONICS SRL

Inventor： DE SANDRE GUIDO ,  PASOTTI MARCO ,  ROLANDI PIER LUIGI

IPC: G11C16/34

Abstract: The optimized soft programming method is used in a memory consisting of a plurality of cells that are grouped into sectors. The cells that belong to a single sector have gate terminals connected to a plurality of word lines, and drain terminals connected to a plurality of local bit lines. The soft programming method consists of selecting at least one local bit line in the sector, and simultaneously selecting all the word lines in the same sector. A corresponding gate voltage is applied to all the word lines, whereas a constant drain voltage, with a pre-determined value is applied to the local bit line.

公开(公告)号：DE69631657D1

公开(公告)日：2004-04-01

申请号：DE69631657

申请日：1996-09-30

Applicant: ST MICROELECTRONICS SRL

Inventor： KRAMER ALAN ,  CANEGALLO ROBERTO ,  ROLANDI PIER LUIGI ,  CHINOSI MAURO ,  GOZZINI GIOVANNI ,  SABATINI MARCO

IPC: G06G7/26 ,  G06N3/063 ,  G11C16/04 ,  G06G7/60

Abstract: The charge injection circuit of this invention comprises at least one pair of floating gate MOS transistors (M1,M2) having source and drain terminals which are coupled together and to an injection node (ND), and at least one corresponding pair of generators (G1,G2) of substantially step-like voltage signals (S1,S2) having an initial value and a final value, and having outputs respectively coupled to the control terminals of said transistors (M1,M2); the signal generators (G1,G2) being such that the initial value of a first (S1) of the signals is substantially the equal of the final value of a second (S2) of the signals, and that the final value of the first signal (S1) is substantially the equal of the initial value of the second signal (S2).

公开(公告)号：DE69628753D1

公开(公告)日：2003-07-24

申请号：DE69628753

申请日：1996-09-30

Applicant: ST MICROELECTRONICS SRL

Inventor： KRAMER ALAN ,  CANEGALLO ROBERTO ,  CHINOSI MAURO ,  GOZZINI GIOVANNI ,  ROLANDI PIER LUIGI ,  SABATINI MARCO

IPC: G11C15/00 ,  G11C15/04

Abstract: An input structure (1) for associative memories, including an array of elementary cells (2), a number of input lines (20), a number of output lines (30), a number of address lines (40), and a number of enabling lines (50). Each elementary cell (2) is formed by a D type latch (3) having a data input connected to one of the address lines (40) and an enabling input connected to one of the enabling lines (50), and by a switch (4) connected between an input line and an output line, and having a control input connected to the output of a respective latch to selectively connect the respective input line (20) and output line (30) according to the data stored in the latch.

公开(公告)号：DE69721252D1

公开(公告)日：2003-05-28

申请号：DE69721252

申请日：1997-09-29

Applicant: ST MICROELECTRONICS SRL

Inventor： PASOTTI MARCO ,  CANEGALLO ROBERTO ,  CHIOFFI ERNESTINA ,  GERNA DANILO ,  ROLANDI PIER LUIGI

IPC: G11C27/00

Abstract: Device for analog programming comprising a current mirror circuit (19) connected to the drain terminals of a cell to be programmed (2) and of a MOS reference transistor (27); an operational amplifier (31) having inputs connected to the drain terminals (13) of the cell (2) and respectively of the MOS transistor (27) and output connected to the control terminal (30) of the MOS transistor. During programming, the control and drain terminals of the cell (2) are biased at corresponding programming voltages and the output voltage of the operational amplifier (31), which is correlated to the current threshold voltage level of the cell (2), is monitored and the programming is interrupted when this output voltage becomes at least equal to a reference voltage correlated to the threshold value desired for the cell.

公开(公告)号：IT1311314B1

公开(公告)日：2002-03-12

申请号：ITTO991098

申请日：1999-12-14

Applicant: ST MICROELECTRONICS SRL

Inventor： DE SANDRE GUIDO ,  PASOTTI MARCO ,  ROLANDI PIER LUIGI

IPC: G11C16/34

Abstract: The optimized soft programming method is used in a memory consisting of a plurality of cells that are grouped into sectors. The cells that belong to a single sector have gate terminals connected to a plurality of word lines, and drain terminals connected to a plurality of local bit lines. The soft programming method consists of selecting at least one local bit line in the sector, and simultaneously selecting all the word lines in the same sector. A corresponding gate voltage is applied to all the word lines, whereas a constant drain voltage, with a pre-determined value is applied to the local bit line.

公开(公告)号：ITTO990942A1

公开(公告)日：2001-04-30

申请号：ITTO990942

申请日：1999-10-29

Applicant: ST MICROELECTRONICS SRL

Inventor： DE SANDRE GUIDO ,  PASOTTI MARCO ,  ROLANDI PIER LUIGI

IPC: G11C16/12

公开(公告)号：ITMI991017A1

公开(公告)日：2000-11-11

申请号：ITMI991017

申请日：1999-05-11

Applicant: ST MICROELECTRONICS SRL

Inventor： PASOTTI MARCO ,  GUAITINI GIOVANNI ,  ROLANDI PIER LUIGI

IPC: G11C11/56 ,  G11C16/34

Abstract: A method for the in-writing verification of the threshold value of the multilevel cells suitable to memorize n bits each, that provides for the utilization of a sense amplifier containing a respective successive approximation register. An output signal of a comparison circuit provides for the loading of the datum to be programmed in the cell being selected, after which a programming pulse is applied and the comparison between the reference current corresponding to said datum and the current that flows in the cell is carried out. The application of the programming pulse and the performance of the comparison are then repeated until it is verified that the current of the cell is smaller than the reference current.