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    12.
    发明专利
    未知

    公开(公告)号：DE602004011195T2

    公开(公告)日：2009-01-08

    申请号：DE602004011195

    申请日：2004-05-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： FERRARA MAURIZIO MARIA ,  MAGRI ANGELO ,  MINOTTI AGATINO

    IPC: H01L23/31 ,  H01L23/495 ,  H01L23/52

    Abstract: A vertical conduction power electronic device package (1) and corresponding assembly method comprising at least a metal frame (2) suitable to house at least a plate or first semiconductor die (16,35) having at least a first (17) and a second conduction terminal (18) on respective opposed sides of the first die (16,35). The first conduction terminal (17) being in contact with said metal frame (2) and comprising at least an intermediate frame (23,24) arranged in contact with said second conduction terminal (18).

    18.
    发明专利
    未知

    公开(公告)号：DE602004011195D1

    公开(公告)日：2008-02-21

    申请号：DE602004011195

    申请日：2004-05-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： FERRARA MAURIZIO MARIA ,  MAGRI ANGELO ,  MINOTTI AGATINO

    IPC: H01L23/31 ,  H01L23/495 ,  H01L23/52

    Abstract: A vertical conduction power electronic device package (1) and corresponding assembly method comprising at least a metal frame (2) suitable to house at least a plate or first semiconductor die (16,35) having at least a first (17) and a second conduction terminal (18) on respective opposed sides of the first die (16,35). The first conduction terminal (17) being in contact with said metal frame (2) and comprising at least an intermediate frame (23,24) arranged in contact with said second conduction terminal (18).

    20.
    发明专利
    未知

    公开(公告)号：DE69631524D1

    公开(公告)日：2004-03-18

    申请号：DE69631524

    申请日：1996-07-05

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MAGRI ANGELO ,  ZAMBRANO RAFFAELE ,  FRISINA FERRUCCIO

    IPC: H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/739

    Abstract: A MOS technology power device comprises a semiconductor substrate (1), a semiconductor layer (2) of a first conductivity type superimposed over the semiconductor substrate (1), an insulated gate layer (5,6,7;51,52,6,7) covering the semiconductor layer (2), a plurality of substantially rectilinear elongated openings (10) parallel to each other in the insulated gate layer, a respective plurality of elongated body stripes (3) of a second conductivity type formed in the semiconductor layer (2) under the elongated openings (10), source regions (4) of the first conductivity type included in the body stripes (3) and a metal layer (9) covering the insulated gate layer and contacting the body stripes and the source regions through the elongated openings. Each body stripe comprises first portions (31) substantially aligned with a first edge of the respective elongated opening and extending under a second edge of the elongated opening to form a channel region, each first portion (31) including a source region (4) extending substantially from a longitudinal axis of symmetry of the respective elongated opening to the second edge of the elongated opening, and second portions (32), longitudinally intercalated with the first portions (31), substantially aligned with the second edge of the elongated opening and extending under the first edge of the elongated opening to form a channel region, each second portion including a source region extending substantially from the longitudinal axis of symmetry to the first edge of the elongated opening, the first portions (31) and second portions (32) of the body stripes (3) being respectively aligned in a direction transversal to the longitudinal axis.

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