中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

20 records (took 0.037 seconds)

    Micro-electro-mechanical structure having electrically insulated regions and manufacturing process thereof
    11.
    发明公开
    Micro-electro-mechanical structure having electrically insulated regions and manufacturing process thereof 有权
    一种微机电结构与电隔离区，以及它们的制备方法

    公开(公告)号：EP1617178A1

    公开(公告)日：2006-01-18

    申请号：EP04425514.9

    申请日：2004-07-12

    Applicant: STMicroelectronics S.r.l.

    Inventor： Spinola Durante, Guido ,  Sassolini, Simone ,  Ferrera, Marco ,  Marchi, Mauro

    IPC: G01C19/56

    CPC classification number: G01C19/5769

    Abstract: Micro-electro-mechanical structure formed by a substrate (41) of semiconductor material and a suspended mass (10, 20) extending above the substrate (41) and separated therefrom by an air gap (55). An insulating region (23, 24) of a first electrically insulating material extends through the suspended mass (10, 20) and divides it into at least one first electrically insulated suspended region and one second electrically insulated suspended region (10a, 10b, 20a, 20b). A plug element (46) of a second electrically insulating material different from the first electrically insulating material is formed underneath the insulating region (23, 24) and constitutes a barrier between the insulating region and the air gap (55) for preventing removal of the insulating region during fabrication, when an etching agent is used for removing a sacrificial layer and forming the air gap.

    Abstract translation: 由半导体材料与悬挂质量（10，20）的基板（41）形成的微机电结构的基片（41）和从通过在空气间隙（55）隔开有上方延伸。 一个第一电绝缘材料制成的绝缘区域（23，24）通过所述悬挂质量（10，20）延伸，并且它分成至少一个第一电绝缘的悬浮区域和至少一个第二电绝缘的悬浮区域（10A，10B，20A， 20B）。 从第一电绝缘材料不同的第二电绝缘材料制成的插头元件（46）被形成在所述绝缘区下面（23，24）和用于防止去除的构成绝缘区域和所述空气间隙（55）之间的阻挡 制造中，当蚀刻剂用于去除牺牲层和形成空气间隙期间绝缘区域。

    Method for manufacturing integrated devices including electromechanical microstructures, without residual stress
    12.
    发明公开
    Method for manufacturing integrated devices including electromechanical microstructures, without residual stress 有权
    一种用于生产具有机电微结构集成器件过程中，没有残余应力

    公开(公告)号：EP1028466A1

    公开(公告)日：2000-08-16

    申请号：EP99830068.5

    申请日：1999-02-09

    Applicant: STMicroelectronics S.r.l.

    Inventor： Ferrari, Paolo ,  Vigna, Benedetto ,  Montanini, Pietro ,  Castoldi, Laura ,  Ferrera, Marco

    IPC: H01L27/00 ,  G01P1/00

    CPC classification number: B81B3/0072 ,  B81B2203/033 ,  B81C1/00666 ,  B81C2201/017 ,  G01P15/0802 ,  G01P2015/0828

    Abstract: On a substrate (20) of semiconductor material, a sacrificial region (21) is formed and an epitaxial layer (25) is grown; then a stress release trench (31) is formed, surrounding an area (33) of the epitaxial layer (25), where an integrated electromechanical microstructure is to be formed; the wafer (28) is then heat treated, to release residual stress. Subsequently, the stress release trench (31) is filled with a sealing region (34) of dielectric material, and integrated components are formed. Finally, inside the area surrounded by the sealing region (34), a microstructure definition trench is formed, and the sacrificial region is removed, thus obtaining an integrated microstructure with zero residual stress.

    Abstract translation: 上的半导体材料的基片（20），牺牲区域（21）被形成和外延层（25）上生长; 外延层（25），其中，在集成式机电微观结构是将要形成的那么应力释放槽（31）形成，周边区域（33）; 晶片（28）进行热处理，以释放残余应力。 接着，应力释放槽（31）中填充有电介质材料制成的密封区域（34），和集成的部件而形成。 最后，通过密封区域（34）包围的区域内，微结构定义沟槽中形成，并且所述牺牲区域被去除，因此，与零张残余应力获得集成微结构。

    Semiconductor device having deep through vias
    15.
    发明公开
    Semiconductor device having deep through vias 有权
    具有深通孔的半导体器件

    公开(公告)号：EP2202791A2

    公开(公告)日：2010-06-30

    申请号：EP10160512.9

    申请日：2005-11-16

    Applicant: STMicroelectronics S.r.l.

    Inventor： Marchi, Mauro ,  Ferrera, Marco ,  Riva, Caterina

    IPC: H01L23/48 ,  H01L21/762

    CPC classification number: B81B7/0006 ,  B81B2201/0242 ,  B81B2201/0257 ,  H01L21/76267 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

    Abstract: A semiconductor device includes a body (1) and, in the body (1): a semiconductor substrate (2), a semiconductor structural layer (10) and a dielectric layer (12) therebetween. A through interconnection via (30) traverses the body (1) and extends through the dielectric layer (12). The through interconnection via (30) has: a front-side interconnection region (17), including a portion of the structural layer (10) that extends between the dielectric layer (12) and a front face (10a) of the body (1) and is laterally insulated from the remainder of the structural layer (10); a back-side interconnection region (27), including a portion of the substrate (2) that extends between the dielectric layer (12) and a back face (2a) of the body (1) and is laterally insulated from the remainder of the substrate (2) by a back-side insulation trench (29). The back-side insulation trench (29) extends across the entire substrate (2; 102; 202), from the back face (2a) of the body (1) to the dielectric layer (12) the; and a conductive continuity region (8) connecting the front-side interconnection region (17) and the back-side interconnection region (27) through the dielectric layer (12).

    Abstract translation: 一种半导体器件包括主体（1），并且在主体（1）中：半导体衬底（2），半导体结构层（10）和其间的介电层（12）。 （30）的直通互连穿过主体（1）并延伸穿过介电层（12）。 （30）的贯穿互连具有：正面互连区域（17），其包括在介电层（12）和主体（1）的正面（10a）之间延伸的结构层（10）的一部分 ）并且与结构层（10）的其余部分横向绝缘; 包括在所述介电层（12）和所述主体（1）的背面（2a）之间延伸的所述衬底（2）的一部分的背侧互连区域（27），并且与所述衬底 衬底（2）通过背侧绝缘沟槽（29）。 背面绝缘沟槽（29）从主体（1）的背面（2a）延伸到整个衬底（2; 102; 202）到介电层（12） 以及通过介电层（12）连接前侧互连区域（17）和后侧互连区域（27）的导电连续区域（8）。

    Process for manufacturing deep through vias in a semiconductor device, and semiconductor device made thereby.
    16.
    发明公开
    Process for manufacturing deep through vias in a semiconductor device, and semiconductor device made thereby. 有权
    Herstellungsprozessfür“deep through vias”in einem Halbleiterbauelement

    公开(公告)号：EP1788624A1

    公开(公告)日：2007-05-23

    申请号：EP05425807.4

    申请日：2005-11-16

    Applicant: STMicroelectronics S.r.l.

    Inventor： Marchi, Mauro ,  Ferrera, Marco ,  Riva, Caterina

    IPC: H01L23/48

    CPC classification number: B81B7/0006 ,  B81B2201/0242 ,  B81B2201/0257 ,  H01L21/76267 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

    Abstract: A process for manufacturing a through via in a semiconductor device includes the steps of: forming a body (1) comprising a structural layer (10), a substrate (2), and a dielectric layer (12) set between the structural layer (10) and the substrate (2); insulating a portion of the structural layer (10) to form a front-side interconnection region (17); insulating a portion of the substrate (2) to form a back-side interconnection region (27); and connecting the front-side interconnection region (17) and the back-side interconnection region (27) through the dielectric layer (12).

    Abstract translation: 在半导体器件中制造通孔的方法包括以下步骤：形成包括结构层（10），基底（2）和设置在结构层（10）之间的介电层（12）的主体（1） ）和基板（2）; 绝缘所述结构层（10）的一部分以形成正面互连区域（17）; 绝缘所述基板（2）的一部分以形成背面互连区域（27）; 并且通过电介质层（12）将前侧互连区域（17）和背面侧互连区域（27）连接起来。

    Process for manufacturing high-sensitivity accelerometric and gyroscopic integrated sensors, and sensor thus produced
    19.
    发明公开
    Process for manufacturing high-sensitivity accelerometric and gyroscopic integrated sensors, and sensor thus produced 失效
    一种用于制造其以这样的方式制造高灵敏度的积分的加速度计和陀螺仪传感器和传感器的方法

    公开(公告)号：EP0895090A1

    公开(公告)日：1999-02-03

    申请号：EP97830407.9

    申请日：1997-07-31

    Applicant: STMicroelectronics S.r.l.

    Inventor： Ferrari, Paolo ,  Vigna, Benedetto ,  Montanini, Pietro ,  Ferrera, Marco

    IPC: G01P15/08 ,  G01P15/125

    CPC classification number: H01L21/764 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81C1/00246 ,  B81C2201/0109 ,  B81C2201/0177 ,  B81C2203/0735 ,  B81C2203/0778 ,  G01P15/0802 ,  G01P15/125 ,  G01P2015/0814 ,  H01L21/76202

    Abstract: To increase the sensitivity of the sensor, the movable mass (40) forming the seismic mass is formed starting from the epitaxial layer (13) and is covered by a weighting region of tungsten (26c) which has high density. To manufacture it, buried conductive regions (2) are formed in the substrate (1); then, at the same time, a sacrificial region is formed in the zone where the movable mass is to be formed and oxide insulating regions (9a-9d) are formed on the buried conductive regions (2) so as to cover them partially; the epitaxial layer (13) is then grown, using a nucleus region; a tungsten layer (26) is deposited and defined and, using a silicon carbide layer (31) as mask, the suspended structure (40) is defined; finally the sacrificial region is removed, forming an air gap (38).

    Abstract translation: 为了提高传感器的灵敏度，在形成振动质量运动质量块（40）形成由具有高密度的外延层（13）和由钨（26C）的加权区域覆盖开始。 为了制造它，掩埋的导电区域（2）在基片（1）形成; 然后，在在Sametime，牺牲区域在可动质量将要形成与氧化物绝缘区域（图9A-9D）是在掩埋的导电区域形成的区域（2）形成，以覆盖它们的部分; 然后在外延层（13）上生长，使用核区; 钨层（26）沉积和定义，并使用碳化硅层（31）作为掩模，对悬挂结构（40）所定义; 最后牺牲区域被移除，在空气间隙（38）形成。

    A method of manufacturing pressure microsensors
    20.
    发明公开
    A method of manufacturing pressure microsensors 失效
    Methode zur Herstellung von mikromechanischen Drucksensoren

    公开(公告)号：EP0863392A1

    公开(公告)日：1998-09-09

    申请号：EP97830093.7

    申请日：1997-03-04

    Applicant: STMicroelectronics S.r.l.

    Inventor： Vigna, Benedetto ,  Ferrari, Paolo ,  Montanini, Pietro ,  Ferrera, Marco

    IPC: G01L9/00

    CPC classification number: G01L9/0054 ,  G01L9/0055

    Abstract: The method described provides for the formation of a region of silicon dioxide on a substrate (11) of monocrystalline silicon, the epitaxial growth of a silicon layer, the opening of holes (14') in the silicon layer above the silicon dioxide region, and the removal of the silicon dioxide which constitutes the region by means of chemical attack through the holes (14') until a silicon diaphragm (12'), attached to the substrate (11) along the edges and separated therefrom by a space (15), is produced. In order to form an absolute pressure microsensor, the space has to be sealed. To do this, the method provides for the holes (14') to have diameters smaller than the thickness of the diaphragm (12') and to be closed by the formation of a silicon dioxide layer (16) by vapour-phase deposition at atmospheric pressure.

    Abstract translation: 所述方法提供了在单晶硅的衬底（11）上形成二氧化硅区域，硅层的外延生长，在二氧化硅区域上方的硅层中的孔（14'）的开口，以及 通过所述孔（14'）的化学侵蚀去除构成所述区域的二氧化硅，直到沿着所述边缘附着到所述基板（11）并通过空间（15）分离的硅隔膜（12'）， ，被生产。 为了形成绝对压力微传感器，必须密封空间。 为此，该方法提供孔（14'）具有小于隔膜（12'）的厚度的直径并且通过在大气中气相沉积形成二氧化硅层（16）来封闭 压力。

Patent Agency Ranking