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    A semiconductor memory
    16.
    发明公开
    A semiconductor memory 审中-公开
    半导体存储器

    公开(公告)号：EP1178491A1

    公开(公告)日：2002-02-06

    申请号：EP00830553.4

    申请日：2000-08-02

    Applicant: STMicroelectronics S.r.l.

    Inventor： Gastaldi, Roberto ,  Cappelletti, Paolo ,  Casagrande, Giulio ,  Campardo, Giovanni ,  Micheloni, Rino

    IPC: G11C16/16 ,  G11C16/34

    CPC classification number: G11C16/3431 ,  G11C16/16 ,  G11C16/34

    Abstract: A semiconductor memory, particularly of the electrically programmable and erasable type such as a flash memory, comprises at least one two-dimensional array (SCT) of memory cells (MC) with a plurality of rows (row0-row511) and a plurality of columns (COL) of memory cells. The columns of the two-dimensional array are grouped in a plurality of packets (CP0-CP1), and the memory cells belonging to the columns of each packet are formed in a respective semiconductor region (4) with a first type of conductivity, this region (4) being distinct from the semiconductor regions (4) with the first type of conductivity in which the memory cells belonging to the columns of the remaining packets are formed. The semiconductor regions with the first type of conductivity divide the set of memory cells belonging to each row into a plurality of subsets of memory cells that constitute elemental memory units which can be modified individually. It is thus possible to produce memory units of very small dimensions (for example, bytes, words, or long words) which can be erased individually, without excessive overhead in terms of area.

    Abstract translation: 半导体存储器，特别是诸如闪存的电可编程和可擦除类型的半导体存储器包括至少一个具有多个行（行0-行511）和多个列的存储器单元（MC）的二维阵列（SCT） （COL）的存储单元。 二维阵列的列被分组为多个分组（CP0-CP1），并且属于每个分组的列的存储器单元以第一类型的导电率形成在相应的半导体区域（4）中，这 区域（4）与半导体区域（4）不同，其中形成属于剩余包的列的存储器单元的第一导电类型。 具有第一导电类型的半导体区域将属于每行的存储器单元组划分为构成可以单独修改的基本存储器单元的多个存储器单元子集。 因此可以产生非常小尺寸的存储单元（例如，字节，单词或长单词），其可以单独擦除，而没有面积方面的过度开销。

    Sensing arrangement for a multilevel semiconductor memory device
    18.
    发明公开
    Sensing arrangement for a multilevel semiconductor memory device 有权
    AusleseanordnungfürMultibit-Halbleiterspeicheranordnung

    公开(公告)号：EP0978844A1

    公开(公告)日：2000-02-09

    申请号：EP98830491.1

    申请日：1998-08-07

    Applicant: STMicroelectronics S.r.l.

    Inventor： Calligaro, Cristiano ,  Rolandi, Paolo ,  Gastaldi, Roberto ,  Torelli, Guido

    IPC: G11C11/56

    CPC classification number: G11C11/5642 ,  G11C11/5621 ,  G11C2211/5634

    Abstract: A multilevel memory device comprises an array of multilevel memory cells (M 1j - M kj , M 1z - M kz ) arranged in rows (WL 1 - WL k ) and columns (BL j , BL z ), each memory cell being capable of being programmed in m = 2 n ( n > 1) distinct programming states, and a sensing arrangement for sensing the memory cells, the sensing arrangement comprising at least ( m - 1) reference columns (BL ref,i , BL ref,h ) of memory cells. The reference columns comprises a number of memory cells substantially identical to the number of memory cells of each column of the array, a smaller number of memory cells (M ref,i , M, ref,h ) of each reference column being multilevel reference memory cells programmed in a respective reference programming state and activatable for sinking a respective reference current (I R,0 ,I R,1 ,I R,2 ), the remaining larger number of memory cells of each reference column being dummy non-conductive memory cells (M dumr,1i - M dumr,ki , M dumr,1h - M dumr,kh ) structurally identical to the reference memory cells and to the memory cells of the array.

    Abstract translation: 多级存储器件包括以行（WL1-WLK）和列（BLj，BLz）排列的多级存储器单元阵列（M1j-Mkj，M1z-Mkz），每个存储器单元能够被编程为m = 2 1）不同的编程状态，以及用于感测存储器单元的感测装置，所述感测装置包括至少（m-1）个存储器单元的参考列（BLref，i，BLref，h）。 参考列包括与阵列的每列的存储单元的数量基本相同的多个存储器单元，每个参考列的较小数量的存储器单元（Mref，i，M，ref，h）是多电平参考存储器单元 编程在相应的参考编程状态并且可激活以吸收相应的参考电流（IR，0，IR，1，IR，2），每个参考列的剩余较大数量的存储单元是虚拟非导电存储器单元（Mdumr， 1i-Mdumr，ki，Mdumr，1h-Mdumr，kh）在结构上与参考存储器单元和阵列的存储器单元相同。

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