公开(公告)号：EP1132959A1

公开(公告)日：2001-09-12

申请号：EP00830162.4

申请日：2000-03-03

Applicant: STMicroelectronics S.r.l.

Inventor： Atti, Massimo ,  Maurelli, Alfonso ,  Zatelli, Nicola

IPC: H01L21/8247 ,  H01L27/115 ,  H01L21/8246

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: The method applies to non-volatile semiconductor memories with cells arranged in rows and in columns, in which each cell has a first terminal (CG), a second terminal (D), and a third terminal (S) connected, respectively, to a row line (WLi), to a column line (BLi), and to a common node by respective connection strips (CG, R). In order to form connections with low resistivity and consequently to save semiconductor area, the method provides for the formation of an oxide layer (I2) which covers the connection strips of the first terminals (CG) and of the third terminals (S), the formation of channels (CH1, CH2) along the connection strips until the surfaces thereof are exposed, and the filling of the channels (CH1, CH2) with a material (W) having a resistivity lower than that of the connection strips.

Abstract translation: 该方法适用于具有排列成行和列的单元的非易失性半导体存储器，其中每个单元具有分别连接到第一端子（CG），第二端子（D）和第三端子（S）的单元 行线（WLi）到列线（BLi），并且通过相应的连接条（CG，R）连接到公共节点。 为了形成具有低电阻率的连接并因此节省半导体面积，该方法提供了覆盖第一端子（CG）和第三端子（S）的连接条的氧化物层（I2）的形成， 沿着连接条形成通道（CH1，CH2），直到其表面露出，并且用具有低于连接条的电阻率的材料（W）填充通道（CH1，CH2）。

公开(公告)号：EP1096575A1

公开(公告)日：2001-05-02

申请号：EP99830629.4

申请日：1999-10-07

Applicant: STMicroelectronics S.r.l.

Inventor： Cappelletti, Paolo ,  Maurelli, Alfonso ,  Zatelli, Nicola

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  H01L27/11558 ,  H01L29/66825 ,  H01L29/7883

Abstract: The memory cell (101) is of the type with a single level of polysilicon, and is produced in a substrate (102) of semiconductor material with a first type of conductivity, and comprises a control gate region (6) with a second type of conductivity, formed in the substrate (102) in a first region of active area (30); regions of source (4a, 4b) and drain (5a, 5b) with the second type of conductivity, formed in the substrate (102) in a second region of active area (31); and a floating gate region (9) which extends transversely relative to the first (30) and the second (31) regions of active area. The control gate region (6) is surrounded by a first well (103) with the first type of conductivity, which in turn is surrounded, below and laterally, by a third well (108) with the second type of conductivity. The regions of source (4a, 4b) and drain (5a, 5b) are accommodated in a second well (104) with the first type of conductivity, which in turn is surrounded below and laterally by a fourth well (112) with the second type of conductivity.

Abstract translation: 存储单元（101）是具有单层多晶硅的类型，并且在具有第一类导电性的半导体材料的衬底（102）中制造，并且包括具有第二类型的多晶硅的控制栅极区域（6） 导电性，形成在有源区域（30）的第一区域中的衬底（102）中; 源极（4a，4b）和具有第二类型导电性的漏极（5a，5b）的区域在有源区域（31）的第二区域中形成在衬底（102）中。 以及相对于有效区域的第一（30）和第二（31）区域横向延伸的浮动栅极区域（9）。 控制栅极区域（6）由具有第一类型导电性的第一阱（103）包围，第一阱具有第二类型的导电性，第三阱又由具有第二类型导电性的第三阱（108）包围。 源极（4a，4b）和漏极（5a，5b）的区域被容纳在具有第一类型导电性的第二阱（104）中，第二阱导电性又被第四阱（112）包围并在第二阱 导电类型。

公开(公告)号：EP1005079A1

公开(公告)日：2000-05-31

申请号：EP98830709.6

申请日：1998-11-26

Applicant: STMicroelectronics S.r.l.

Inventor： Cappelletti, Paolo Giuseppe ,  Maurelli, Alfonso

IPC: H01L21/8239 ,  H01L27/105

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11546 ,  Y10S438/981

Abstract: A process for the manufacturing of an integrated circuit including a low operating voltage, high-performance logic circuitry and an embedded memory device having a high operating voltage higher than the low operating voltage of the logic circuitry, providing for: on first portions of a semiconductor substrate (1), forming a first gate oxide layer (3) for first transistors operating at the high operating voltage; on second portions of the semiconductor substrate (1), forming a second gate oxide layer (5) for memory cells of the memory device; on the first and second gate oxide layers (3,5), forming from a first polysilicon layer (6) gate electrodes (8,9) for the first transistors, and floating-gate electrodes (7) for the memory cells; forming over the floating-gate electrodes (7) of the memory cells a dielectric layer (18); on third portions of the semiconductor substrate (1), forming a third gate oxide layer (24) for second transistors operating at the low operating voltage; on the dielectric layer (18) and on the third portions of the semiconductor substrate (1), forming from a second polysilicon layer (25) control gate electrodes (29) for the memory cells, and gate electrodes (26,27) for the second transistors; in the first portions of the semiconductor substrate (1), forming source and drain regions (12,13;16,17) for the first transistors; in the second portions of the semiconductor substrate (1), forming source and drain regions (30,31) for the memory cells; in the third portions of the semiconductor substrate (1), forming source and drain regions for the second transistors.

Abstract translation: 一种用于制造集成电路的方法，该集成电路包括低工作电压，高性能逻辑电路和具有高于逻辑电路的低工作电压的高工作电压的嵌入​​式存储器件，其提供：在半导体的第一部分上 衬底（1），形成用于在高工作电压下工作的第一晶体管的第一栅极氧化物层（3） 在所述半导体衬底（1）的第二部分上形成用于所述存储器件的存储器单元的第二栅极氧化物层（5）; 在第一和第二栅极氧化物层（3,5）上形成第一晶体管的第一多晶硅层（6）用于第一晶体管的栅电极（8,9）和用于存储单元的浮栅电极（7）; 在存储单元的浮栅电极（7）上形成介电层（18）; 在半导体衬底（1）的第三部分上形成用于在低工作电压下工作的第二晶体管的第三栅极氧化物层（24）; 在所述电介质层（18）和所述半导体衬底（1）的所述第三部分上，从第二多晶硅层（25）形成用于存储单元的栅极电极（29）和用于所述存储单元的栅电极（26,27） 第二晶体管; 在半导体衬底（1）的第一部分中，形成用于第一晶体管的源区和漏区（12,13; 16,17） 在半导体衬底（1）的第二部分中，形成用于存储单元的源区和漏区（30,31）; 在半导体衬底（1）的第三部分中，形成用于第二晶体管的源极和漏极区域。

公开(公告)号：EP0961285A1

公开(公告)日：1999-12-01

申请号：EP98830333.5

申请日：1998-05-29

Applicant: STMicroelectronics S.r.l.

Inventor： Campardo, Giovanni ,  Micheloni, Rino ,  Maurelli, Alfonso

IPC: G11C7/06 ,  G11C16/06

CPC classification number: G11C16/28 ,  G11C7/06 ,  G11C7/062

Abstract: The reading method comprises the steps of: supplying simultaneously two memory cells (F1, F2), both storing a respective unknown charge condition; generating two electrical quantities (Va, Vb), each correlated to a respective charge condition; comparing the two electrical quantities (Va, Vb) with each other; and generating a two-bit signal (01, 02) on the basis of the result of the comparison. The reading circuit comprises a two-input comparator (58) comprising two branches in parallel, each branch being connected to a respective memory cell by a current/voltage converter (41). Both the two-input comparator (58) and the current/voltage converter (41) comprise low threshold transistors (49, 50, 65-68).

Abstract translation: 读取方法包括以下步骤：同时提供两个存储相应的未知充电条件的存储单元（F1，F2） 产生两个电量（Va，Vb），每个电量与相应的充电条件相关; 将两个电量（Va，Vb）彼此进行比较; 并根据比较结果生成2比特信号（01,02）。 读取电路包括并联的两个分支的双输入比较器（58），每个分支通过电流/电压转换器（41）连接到相应的存储单元。 双输入比较器（58）和电流/电压转换器（41）都包括低阈值晶体管（49,50,65-68）。

公开(公告)号：EP0643418B1

公开(公告)日：1998-12-02

申请号：EP93830365.8

申请日：1993-09-10

Applicant: STMicroelectronics S.r.l.

Inventor： Ghezzi, Paolo ,  Maurelli, Alfonso

IPC: H01L21/329 ,  H01L29/866 ,  H01L27/06

CPC classification number: H01L29/66106 ,  H01L27/0629 ,  H01L29/866 ,  Y10S148/174 ,  Y10S438/983

公开(公告)号：EP1505653A1

公开(公告)日：2005-02-09

申请号：EP03425532.3

申请日：2003-08-04

Applicant: STMicroelectronics S.r.l.

Inventor： Cappelletti, Paolo Giuseppe ,  Maurelli, Alfonso ,  Zabberoni, Paola

IPC: H01L27/115

CPC classification number: H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11546

Abstract: A method for manufacturing electrically non-active structures of an electronic circuit integrated on a semiconductor substrate (5) comprising first electrically active structures (6) and second electrically active structures (7), comprising the steps of:

inserting, in the electronic circuit, electrically non-active structures (8) to uniform the surface of the electronic circuit, the method being characterised in that it comprises the following further steps:
identifying, between the electrically non-active structures (8), a first group (9) of electrically non-active structures adjacent to the first (6) and second (7) electrically active structures,
identifying, between the electrically non-active structures (8), a second group (10) of electrically non-active structures not adjacent to the first (6) and second (7) electrically active structures,
defining, on the semiconductor substrate, the first (9) and second (10) group of electrically non-active structures through different photolithographic steps.

Abstract translation: 一种用于制造集成在包括第一电活动结构（6）和第二电活动结构（7）的半导体衬底（5）上的电子电路的电非活性结构的方法，包括以下步骤：在电子电路中， 电非电活动结构（8）以使电子电路的表面均匀，该方法的特征在于其包括以下进一步的步骤：在电非活性结构（8）之间识别第一组（9） 与第一（6）和第二（7）电活性结构相邻的电非活性结构，在电非活性结构（8）之间识别不邻近第一电活性结构（8）的电非活性结构的第二组（10） 第一（6）和第二（7）电活性结构，在半导体衬底上通过不同的光电层限定第一（9）和第二（10）组电非活性结构 书写步骤

公开(公告)号：EP1480271A1

公开(公告)日：2004-11-24

申请号：EP03425336.9

申请日：2003-05-23

Applicant: STMicroelectronics S.r.l.

Inventor： Cappelletti, Paolo ,  Maurelli, Alfonso

IPC: H01L23/544 ,  G01R31/316

CPC classification number: H01L22/34 ,  G01R31/2853 ,  G01R31/2884 ,  G11C29/02 ,  G11C29/022 ,  G11C29/025 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A test chip has been conceived to perform all the measurements needed to evaluate the performances of interconnects (in particular, to measure the statistical failure distribution, the electromigration, and the leakage current), and an algorithm has been developed to detect the via failure at any of the available n metal layers. The test chip consists basically of a ROM memory array. The vias to be measured are realized in the columns of the array. Vias (or contact) failures are detected by forcing a predetermined current through both an array column and a reference column. The required failure analysis is attained by comparing the resulting voltage drops.

Abstract translation: 测试芯片已经设想来执行所有评估互连的性能（特别地，以测量统计故障分布，电迁移，和泄漏电流）所需的测量，并在算法已经被开发，以检测通过故障在 任何可用金属ñ层。 测试芯片的基本上是一个ROM存储器阵列的besteht。 所述通孔是在所述阵列的列进行测量实现。 通孔（或触点）故障是通过迫使电流流过预定的两个阵列列和一个参考列的检测。 所需的故障分析是通过比较所得到的电压降获得的。

公开(公告)号：EP0961285B1

公开(公告)日：2003-12-17

申请号：EP98830333.5

申请日：1998-05-29

Applicant: STMicroelectronics S.r.l.

Inventor： Campardo, Giovanni ,  Micheloni, Rino ,  Maurelli, Alfonso

IPC: G11C7/06 ,  G11C16/06

CPC classification number: G11C16/28 ,  G11C7/06 ,  G11C7/062

公开(公告)号：EP1253635A1

公开(公告)日：2002-10-30

申请号：EP01830267.9

申请日：2001-04-23

Applicant: STMicroelectronics S.r.l.

Inventor： Crivelli, Barbara ,  Alessandri, Mauro ,  Servalli, Giorgio ,  Maurelli, Alfonso

IPC: H01L21/8247 ,  H01L21/336

CPC classification number: H01L27/11521 ,  H01L29/66825

Abstract: The present invention relates to a method for sealing a nonvolatile memory device, characterized in that to comprise the following steps of: a) defining a nonvolatile memory cell (20), being composed by the overlap of a tunnel oxide (3), of a floating gate (1), of an interpoly dielectric (2), and of a control gate (4); b) deposing a silicon oxide layer (11) by a CVD (Chemical Vapor Deposition) at a temperature lower than 1000 °C on said control gate (4); c) densifing said silicon oxide layer (11) by a further thermal treatment (13). (Figure 5).

Abstract translation: 非易失性存储器件的密封方法技术领域本发明涉及一种用于密封非易失性存储器件的方法，其特征在于包括以下步骤：a）限定由隧道氧化物（3）的重叠构成的非易失性存储单元（20） 互补电介质（2）和控制栅极（4）的浮栅（1）; b）通过CVD（化学气相沉积）在所述控制栅极（4）上在低于1000℃的温度下沉积氧化硅层（11）; c）通过进一步的热处理（13）使所述氧化硅层（11）致密化。 （图5）。

公开(公告)号：EP1139419A1

公开(公告)日：2001-10-04

申请号：EP00830236.6

申请日：2000-03-29

Applicant: STMicroelectronics S.r.l.

Inventor： Peschiaroli, Daniela ,  Maurelli, Alfonso ,  Palumbo, Elisabetta ,  Piazza, Fausto

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/11526 ,  H01L27/1052 ,  H01L27/11541

Abstract: Method of manufacturing an integrated circuit comprising a memory operating at high voltage and logic circuitry operating at a lower voltage than the memory:
   formation of a first layer of gate oxide (3) with a first thickness on first and second portions of a semiconductor substrate (1) which are intended, respectively, for first transistors operating at high voltage and for second transistors operating at the lower voltage, and formation of a second layer of gate oxide (5) with a second thickness on third portions for cells of the memory; deposition of a first polysilicon layer to define gate electrodes (8,9) for first transistors and floating gate electrodes (7) for the memory cells; deposition of an interpolysilicon dielectric layer (18) so as to leave the interpolysilicon dielectric layer on the gate electrodes (8,9) of first transistors and on the floating gate electrodes (7); formation, on the second portions (1), of a third gate oxide layer (24) with a third thickness less than the first thickness of the first gate oxide layer (3); deposition of a second polysilicon layer (25) to define gate structures (29) of the memory cells, and gate electrodes (26,27) of second transistors and polysilicon covers (80,90) for the gate electrodes (8,9) of first transistors.

Abstract translation: 一种制造集成电路的方法，该集成电路包括在高电压下工作的存储器和在比该存储器低的电压下操作的逻辑电路：在半导体衬底的第一和第二部分上形成具有第一厚度的栅极氧化物（3）的第一层 1），其分别用于在高电压下操作的第一晶体管和用于在较低电压下操作的第二晶体管，以及在存储器的单元的第三部分上形成具有第二厚度的栅极氧化物（5）的第二层; 沉积第一多晶硅层以限定用于第一晶体管的栅电极（8,9）和用于存储器单元的浮栅电极（7）; 沉积多晶硅介电层（18），以便在第一晶体管的栅电极（8,9）和浮栅电极（7）上留下多晶硅介电层; 在第二部分（1）上形成具有小于第一栅极氧化物层（3）的第一厚度的第三厚度的第三栅极氧化物层（24）; 沉积第二多晶硅层（25）以限定存储器单元的栅极结构（29），以及第二晶体管的栅电极（26,27）和用于栅电极（8,9）的多晶硅覆盖物（80,90） 第一晶体管。