公开(公告)号：EP3744576A1

公开(公告)日：2020-12-02

申请号：EP20170928.4

申请日：2020-04-22

Applicant: STMicroelectronics S.r.l.

Inventor： RAGONE, Giancarlo ,  POLETTO, Vanni

IPC: B60R21/017

Abstract: A drive circuit (10) for airbag systems, for instance comprises:
- a differential transconductance amplifier (14) having a first input node (146), a second input node (144), an output node (140), the output node (140) coupled to the second input node (144) via a feedback line (142),
- a supply node (101) and a drive node (103) configured to be coupled to the current path through a transistor (PT) with the transistor intermediate the supply node (101) and the drive node (103), the supply node (101) configured to be coupled to a power supply source (VS),
- a control node (102) configured to be coupled to the control electrode of the transistor (PT), the control node (102) coupled to the output node (140) of the differential transconductance amplifier (14),
- a zener diode arrangement (16) having cathode and anode terminals coupled to the supply node (101) and the first input node (146) of the differential transconductance amplifier (14),
- a pull-up component (20, 20') arranged in parallel to the zener diode arrangement (16), and
- an enable switch (18) coupled to the first input node (146) of the differential transconductance amplifier (14), the enable switch (18) referred to ground (GND) and switchable (E) between a conductive state and a non-conductive state with the differential transconductance amplifier (14) providing controlled current discharging/charging of the control node (102) to make the transistor (PT) conductive/non-conductive, respectively.

公开(公告)号：EP3575810B1

公开(公告)日：2020-08-05

申请号：EP19175888.7

申请日：2019-05-22

Applicant: STMicroelectronics S.r.l.

Inventor： PENNISI, Orazio ,  BENDOTTI, Valerio ,  POLETTO, Vanni

IPC: G01R31/396

公开(公告)号：EP3208940B1

公开(公告)日：2018-12-05

申请号：EP16191058.3

申请日：2016-09-28

Applicant: STMicroelectronics S.r.l.

Inventor： ZELLA, Daniele ,  POLETTO, Vanni ,  FOPPIANI, Mauro

IPC: G05F3/26 ,  H03K17/60 ,  H03K17/687

CPC classification number: H03K17/6872 ,  G05F3/26 ,  H03K17/60 ,  H03K17/687

Abstract: In one embodiment, a (pre)driver circuit (10) includes first (10a) and a second (10b) output terminal for driving electronic switches, such as e.g. MOSFETs (S) including a control terminal (GN, GP) and a e.g. source-drain current path through the switch (SN, SP), the arrangement admitting: - one or more first driving configurations (e.g. for PMOS), with the first (10a) and second (10b) output terminals are coupled to the current path (SP) and the control electrode (GP) of the electronic switch (S), respectively, and - one or more second driving configurations (e.g. for NMOS, both HS and LS), wherein the first (10a) and second (10b) output terminals of the driver circuit (10) are coupled to the control electrode (GN) and the current path (SN) of the electronic switch, respectively.

公开(公告)号：EP4293864A1

公开(公告)日：2023-12-20

申请号：EP23175108.2

申请日：2023-05-24

Applicant: STMicroelectronics S.r.l.

Inventor： MARZO, Alberto ,  RANDAZZO, Vincenzo ,  POLETTO, Vanni ,  SUSINNA, Giovanni

IPC: H02J7/00

Abstract: A capacitance (Cload) coupled to a source of electrical charge (S) via a drain-source current flow path through a field-effect transistor (M1), is precharged by making the field-effect transistor (M1) selectively conductive in response to the gate-source voltage (Vgs) of the field-effect transistor (M1) exceeding an (e.g., temperature-dependent) threshold (Vth). The difference between the gate-source voltage (Vgs) of the field-effect transistor (M1) and the threshold (Vth) provides an overdrive value of the field-effect transistor (M1). The gate of the field-effect transistor (M1) is driven with a variable gate-source voltage (Vgs) having as a target maintaining a constant overdrive value. Electrical charge is thus controllably transferred from the source (S) to the capacitance (Cload) via the drain-source current flow path through the field-effect transistor (M1) avoiding undesirably high inrush currents and hot spotting.

公开(公告)号：EP4277130A1

公开(公告)日：2023-11-15

申请号：EP23164784.3

申请日：2023-03-28

Applicant: STMicroelectronics S.r.l.

Inventor： POLETTO, Vanni ,  LOI, Fabrizio

IPC: H03K17/082

Abstract: A method, comprising: coupling a high-side switching transistor (Q HS ) between a high-side reference node (Vs) and a switching node (V OUT ), coupling a low-side switching transistor (Q LS ) between the switching node (V OUT ) and a low-side reference node (GND); coupling an inductive load (L, Z L ) to the switching node (V OUT ) and to a reference node among the high-side reference node (Vs) and the low-side reference node (GND), arranging the respective high-side switch (Q HS ) or low-side switch (Q LS ) to be freewheeling as a result, coupling an inductive load (L, Z L ) to the switching node (V OUT ) and to a reference node selected out of the high-side reference node (Vs) and the low-side reference node (GND), with a respective one of the high-side switching transistor (Q HS ) or low-side switching transistor (Q LS ) being freewheeling as a result, and in response to a short circuit occurring at the switching node (V OUT ) with the respective freewheeling switching transistor (Q HS , Q LS ) in the conductive state: sensing (22; M S ) an electrical signal (V OUT ; I HS ; I LS ) at the switching node (V OUT ), performing a comparison (22) between the electrical signal (V OUT ; I HS ; I LS ) sensed at the switching node (V OUT ) and a threshold level (I REF , V TH , 23; 23A), and providing a driving signal (CMP; 24, 26, 21) to the control node of the respective freewheeling switching transistor to switch the respective freewheeling switching transistor (Q HS , Q LS ) to the non-conductive state as a result of the comparison indicating that the electrical signal (I HS ; I LS ) has reached the threshold level (I REF , V TH , 23; 23A).

公开(公告)号：EP4246179A1

公开(公告)日：2023-09-20

申请号：EP23158628.0

申请日：2023-02-24

Applicant: STMicroelectronics S.r.l.

Inventor： LEONE, Antonio Davide ,  POLETTO, Vanni

IPC: G01S7/524 ,  G01S15/10 ,  G01S15/931 ,  B06B1/02 ,  G01S7/52

Abstract: An ultrasound transmitter device for driving piezoelectric transducers,
comprising a central-tap transformer (11) and a piezoelectric transducer (12) coupled to the terminals of the secondary output winding of said central-tap transformer (11) from which it receives a controlled current (Ip),
said central-tap transformer (11) comprising a primary winding, which includes terminals (DRV1, DRV2) at the ends of said primary winding and a central terminal (DRVC), said central terminal (DRVC) being coupled to a constant d.c. voltage, in particular a battery voltage (VBAT), said end terminals (DRV1, DRV2) being coupled, through respective transistors (Q1, Q2), in particular MOSFETs, which operate in push-pull mode, to a ground voltage (GND), said transistors (Q1, Q2) operating in push-pull mode being driven into their own open and closed states by respective complementary pulse sequences (SP, SPn), wherein:
said transmitter device (20) comprises a digital-to-analog converter (21), which supplies an analog current (Idac) to a driving amplifier (22) configured for determining the flowing of a driving current (Iout) in said transistors (Q1, Q2) operating in push-pull mode,
said transistors (Q1, Q2) operating in push-pull mode are coupled to said ground terminal (GND) through a sense resistance (Rsense),
the output of said digital-to-analog converter (21) is coupled to an input terminal (NR) of the driving amplifier (22), which is also coupled to the ground terminal (GND) through a reference resistance (Rref) having a value proportional to, in particular a multiple or a divisor of, the value of the sense resistance (Rsense),
said sense resistance (Rsense) being coupled to the other input terminal of the driving amplifier (22).

公开(公告)号：EP4137366A3

公开(公告)日：2023-05-03

申请号：EP22190946.8

申请日：2022-08-18

Applicant: STMicroelectronics S.r.l.

Inventor： ARGENTO, Davide ,  PENNISI, Orazio ,  CASTORINA, Stefano ,  POLETTO, Vanni ,  LANDINI, Matteo ,  MAINO, Andrea

IPC: B60R21/017 ,  G01R27/26 ,  G01R31/00 ,  G01R31/64 ,  B60R21/01

Abstract: A system and method for measuring a capacitance value of a capacitor (102) are provided. In embodiments, a resistor (112) is coupled to a terminal of the capacitor (102). A difference in voltage at the terminal between a first time and a second time during a discharge routine of the capacitor (102) is measured. The discharge routine includes sinking a current through a discharge circuit (108, 110) coupled to the resistor (112) from first to second. Integration of a difference in voltage at terminals of the resistor (112) during the discharge routine between the first and second times is also measured. The capacitance value is computed based on the measured difference in voltage, the measured integration, and the resistance value of the resistor (112). The health of the capacitor (102) is determined based on a difference between the computed capacitance value and a threshold value.

公开(公告)号：EP4137824A1

公开(公告)日：2023-02-22

申请号：EP22190928.6

申请日：2022-08-18

Applicant: STMicroelectronics S.r.l.

Inventor： ARGENTO, Davide ,  PENNISI, Orazio ,  CASTORINA, Stefano ,  POLETTO, Vanni ,  LANDINI, Matteo ,  MAINO, Andrea

IPC: G01R27/26 ,  B60R21/017 ,  G01R31/00 ,  G01R31/64 ,  B60R21/01

Abstract: A system and method is provided for measuring a voltage drop at a node (V IN ). In embodiments, a circuit includes an analog-to-digital converter (402), a current sink (406), and a controller. The input of the analog-to-digital converter (402) and the input of the current sink (406) is coupled to the node (V IN ) to be measured. A set point for the current sink (406) is determined. The output of the analog-to-digital converter (402) during the voltage drop is sampled. And a relative voltage drop value is computed by subtracting the sampled output of the analog-to-digital converter (402) during the voltage drop from a sampled output of the analog-to-digital converter (402) during a steady-state condition. The current sink (406) operating at the set point during the steady-state condition and during the voltage drop.

公开(公告)号：EP3937317A1

公开(公告)日：2022-01-12

申请号：EP21305823.3

申请日：2021-06-16

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS

Inventor： LETOR, Romeo ,  POLETTO, Vanni ,  PAVLIN, Antoine ,  RUSSO, Alfio ,  LECCI, Nadia

IPC: H01S5/042 ,  H01S5/062 ,  H03K17/56 ,  G01S17/88

Abstract: A pulse generator circuit, for driving an array of laser diodes (LD_1, ..., LD_n) in a LIDAR system, for instance, comprises an LC resonant circuit (Lr, Cr) coupled between a first node (12) and a reference node (GND) as well as charge circuitry (16) configured to charge the capacitance (Cr) in the LC resonant circuit (Lr, Cr). A first electronic switch (S1) is coupled between the first node (12) and the reference node (GND), and one or more second electronic switches (S2_1, ..., S2_n) are coupled between the first node (12) and respective drive nodes (12 1 , ..., 12 n ) in turn configured to be coupled to respective electrical loads (LD_1, ..., LD_n).
The circuit comprises drive circuitry (18, 182_1, ..., 182_n; 201, 202, 203) configured to repeat pulse generation cycles comprising:
closing the first electronic switch (S1), to enable the LC resonant circuit (Lr, Cr) to oscillate with an increasing current flowing in the inductance (Lr) therein,
in response to the current flowing in the inductance (Lr) reaching a threshold value, opening the first electronic switch (S1) wherein, as a result of one second electronic switch (S2_1, ..., S2_n) being closed for a respective pulse duration time (Ton_S2_1, ..., Ton_S2_n), the current in the inductance (Lr) is commutated towards the aforesaid second electronic switch (S2_1, ..., S2_n) and the respective drive node (12 1 , ..., 12 n ),
opening the at least one second electronic switch (S2_1, ..., S2_n) at the expiration of said respective pulse duration time (Ton_S2_1, ..., Ton_S2_n).

公开(公告)号：EP3648349A1

公开(公告)日：2020-05-06

申请号：EP19203837.0

申请日：2019-10-17

Applicant: STMicroelectronics S.r.l.

Inventor： POLETTO, Vanni ,  ALAGNA, Diego ,  ERRICO, Nicola ,  CIGNOLI, Marco ,  DE AGOSTINI, Gian Battista

IPC: H03K7/08 ,  H02M3/157

Abstract: A PWM signal generator (12) configured (D) to provide a supply current (I LOAD ) to an electrical load (L) generates PWM signals at a first frequency (f PWM ), the PWM signals having a duty cycle.
Operating the generator involves:
- receiving a set point signal (SP) indicative of a target average value for the supply current (I LOAD ),
- sensing (20) a sensing signal indicative of a current actual value of the supply current (I LOAD ),
- performing a closed-loop control of the supply current (I LOAD ) targeting the target value (SP) for the supply current via a controller (14; 141, 142, 143, 144) such as a PID Controller which controls (PID) the duty cycle of the PWM signals generated by the PWM signal generator (12) as a function of the offset (18) of the sensing signal with respect to the set point signal (SP).