公开(公告)号：EP2096448A3

公开(公告)日：2012-04-04

申请号：EP09161586.4

申请日：2005-01-25

Applicant: STMicroelectronics S.r.l.

Inventor： Combi, Chantal ,  Baldo, Lorenzo ,  Faralli, Dino ,  Villa, Flavio Francesco

IPC: G01P15/12 ,  G01P15/08 ,  G01P15/18

CPC classification number: G01P15/123 ,  G01P15/0802 ,  G01P15/18 ,  G01P2015/084

Abstract: A manufacturing process of a combined semiconductor accelerometer and pressure-monitoring device (30) is disclosed, envisaging: providing a wafer (31) of semiconductor material; providing, in a first region (34a) of the wafer (31) a first buried cavity (22) and a first membrane (23), suspended over, and closing at the top, the first buried cavity (22); providing, in a second region (34b) of the wafer (31), a second buried cavity (40) and a second membrane (41), suspended over, and closing at the top, the second buried cavity (40); coupling an inertial mass (25) in a rigid way to the first membrane (23), by forming the inertial mass (25) on top of a surface of the first membrane (23) opposite to the first buried cavity (22); providing, in the first membrane (23), first piezoresistive transduction elements (24) sensitive to strains of the first membrane (23) due to movements of the inertial mass (25) in response to a sensed acceleration and generating corresponding electrical signals, so as to provide an acceleration sensor (35); and providing, in the second membrane (41), second piezoresistive transduction elements (42) sensitive to strains of the second membrane (41) in response to a sensed pressure and generating corresponding electrical signals, so as to provide a pressure sensor (36) integrated with the acceleration sensor (35) in the wafer (31). A combined semiconductor accelerometer and pressure-monitoring device (30) is also disclosed, made with the above manufacturing process.

公开(公告)号：EP1881527A1

公开(公告)日：2008-01-23

申请号：EP06425494.9

申请日：2006-07-17

Applicant: STMicroelectronics S.r.l.

Inventor： Barlocchi, Gabriele ,  Corona, Pietro ,  Villa, Flavio Francesco

IPC: H01L21/762

CPC classification number: H01L21/76264 ,  H01L21/7682

Abstract: A process for manufacturing a semiconductor wafer including SOI-insulation wells envisages forming, in a die region (5; 105) of a semiconductor body (2, 17; 102, 117), buried cavities (20, 21, 22; 110', 111', 112') and semiconductor structural elements (13', 14', 15'; 113', 114', 115'), which traverse the buried cavities and are distributed in the die region (5; 105). The process moreover includes the step of oxidizing selectively first adjacent semiconductor structural elements (13'; 113'), arranged inside a closed region (6; 106), and preventing oxidation of second semiconductor structural elements (14'; 114') outside the closed region (6; 106), so as to form a die buried dielectric layer (29; 129) selectively inside the closed region (6; 106).

Abstract translation: 半导体本体的;一种用于制造半导体晶片包含SOI绝缘井设想形成，在一个区域（105 5）方法（2，17; 102，117），埋空腔（20，21，22; 110”， 111 '112 '）和半导体结构元件（13'，14' ，15 '; 113'，114'，115' ），其穿过所述掩埋腔和分布在区域（5; 105）。 该方法更超过包括氧化步骤选择性第一相邻的半导体结构元件（13”，113‘），一个封闭的区域（6; 106）内设置的外部，和第二半导体结构元件防止氧化（14’，114' ） 闭区域（6; 106），以便形成一个掩埋介电层，其中（29; 129）选择性地将所述闭合区域（6; 106）的内部。

公开(公告)号：EP1798764A1

公开(公告)日：2007-06-20

申请号：EP05425885.0

申请日：2005-12-14

Applicant: STMicroelectronics S.r.l.

Inventor： Ottaviani, Giampiero c/o Masem ,  Corni, Federico c/o Masem ,  Ferrari, Paolo ,  Villa, Flavio Francesco

IPC: H01L21/762

CPC classification number: H01L21/76254

Abstract: In order to manufacture a layer (15) of semiconductor material, a first wafer (1) of semiconductor material is subjected to implantation to form a defect layer (6) at a distance from a first face; the first wafer is bonded to a second wafer (10), by putting an insulating layer present on the second wafer in contact with the first face of the first wafer. Then, hydrogen atoms (13) are introduced into the first wafer (1) through a second face (3) at an energy such as to avoid defects to be generated in the first wafer and at a temperature lower than 600°C. Thereby, the first wafer splits into a usable layer (15), bonded to the second wafer (10), and a remaining layer (16) comprised between the defect layer (6) and the second face of the first wafer. Prior to bonding, the first wafer is subjected to processing steps for obtaining integrated components (7).

Abstract translation: 为了制造半导体材料层（15），对半导体材料的第一晶片（1）进行注入以形成距离第一面一定距离的缺陷层（6）; 通过将存在于第二晶片上的绝缘层与第一晶片的第一面接触来将第一晶片接合到第二晶片（10）。 然后，氢原子（13）通过第二面（3）以能量被引入到第一晶片（1）中，以避免在第一晶片中以及在低于600℃的温度下产生缺陷。 由此，第一晶片分裂成与第二晶片（10）接合的可用层（15），以及包含在缺陷层（6）和第一晶片的第二面之间的剩余层（16）。 在接合之前，第一晶片经受用于获得集成部件（7）的处理步骤。

公开(公告)号：EP1770055A1

公开(公告)日：2007-04-04

申请号：EP05425676.3

申请日：2005-09-28

Applicant: STMicroelectronics S.r.l.

Inventor： Corona, Pietro ,  Villa, Flavio Francesco ,  Barlocchi, Gabriele

IPC: B81B3/00

CPC classification number: B81C1/00158 ,  B81B2201/025 ,  B81B2203/0109 ,  B81B2203/0315

Abstract: A process for manufacturing a suspended structure (20) of semiconductor material envisages the steps of: providing a monolithic body (10) of semiconductor material having a front face (10a); forming a buried cavity (17) within the monolithic body (10), extending at a distance from the front face (10a) and delimiting, with the front face (10a), a surface region (18) of the monolithic body (10), said surface region (18) having a first thickness (w 1 ); carrying out a thickening thermal treatment such as to cause a migration of semiconductor material of the monolithic body (10) towards the surface region (18) and thus form a suspended structure (20) above the buried cavity (17), the suspended structure (20) having a second thickness (w 2 ) greater than the first thickness (w 1 ). The thickening thermal treatment is an annealing treatment.

Abstract translation: 一种用于制造半导体材料的悬浮结构（20）方法设想的以下步骤：提供半导体材料的整体式主体（10），其具有前表面（10A）; 形成在从所述前表面（10a）的延伸一段距离并限定，与所述整体式主体的前表面（10a）中，表面区域（18）的整体式主体内的掩埋空腔（17）（10）（10） 具有第一厚度（W 1）所述的表面区域（18）; 进行增稠热处理：如，以使整体式主体（10）朝向所述表面区域（18）并且因此半导体材料的迁移形成掩埋空腔（17）之上的悬挂结构（20），所述悬挂结构（ 20）具有第二厚度（W 2）比所述第一厚度更大的（W 1）。 增稠热处理是退火处理。

公开(公告)号：EP1577656A1

公开(公告)日：2005-09-21

申请号：EP04425197.3

申请日：2004-03-19

Applicant: STMicroelectronics S.r.l.

Inventor： Villa, Flavio Francesco ,  Barlocchi, Gabriele ,  Corona, Pietro ,  Vigna, Benedetto ,  Baldo, Lorenzo

IPC: G01L9/00

CPC classification number: G01L9/0073 ,  G01L9/0045

Abstract: Method for manufacturing a semiconductor pressure sensor, wherein, in a silicon substrate (2), trenches (6a) are dug and delimit walls (7a); a closing layer (10) is epitaxially grown, that closes the trenches (6a) at the top and forms a suspended membrane (13); a heat treatment is performed so as to cause migration of the silicon of the walls (7a) and to form a closed cavity (11) underneath the suspended membrane; and structures (25a, 25b, 26a-26d) are formed for transducing the deflection of the suspended membrane (13) into electrical signals.

公开(公告)号：EP1541991A1

公开(公告)日：2005-06-15

申请号：EP03425800.4

申请日：2003-12-12

Applicant: STMicroelectronics S.r.l.

Inventor： Mastromatteo, Ubaldo ,  Villa, Flavio Francesco ,  Barlocchi, Gabriele

IPC: G01N21/25 ,  G01N21/64 ,  B01L3/00 ,  B81B3/00 ,  B01J19/00

CPC classification number: G01N21/6428 ,  B01J19/0093 ,  B01J2219/0097 ,  B01L3/502707 ,  B01L3/502715 ,  B01L7/52 ,  B01L2200/12 ,  B01L2300/0654 ,  B01L2300/0816 ,  G01N21/6454

Abstract: An integrated semiconductor chemical microreactor (21) for real-time polymerase chain reaction (PCR) monitoring, has a monolithic body (2) of semiconductor material; a number of buried channels (3) formed in the monolithic body (2); an inlet trench (14) and an outlet trench (15) for each buried channel (3); and a monitoring trench (16) for each buried channel (3), extending between the inlet and outlet trenches (14, 15) thereof from the top surface (4) of the monolithic body (2) to the respective buried channel (3). Real-time PCR monitoring is carried out by channeling light beams into the buried channels (3), whereby the light beams impinge on the fluid therein, and by collecting and processing light beams coming out from the monitoring trenches (16) and emitted by the fluid within the buried channels (3).

Abstract translation: 实时聚合酶链式反应（PCR）监测的集成半导体化学微反应器（21），具有半导体材料的整体式主体（2）; 在整体式主体形成多个掩埋信道（3）（2）; 在入口沟槽（14）和在出口处的沟槽（15），用于各掩埋沟道（3）; 并为每个掩埋沟道的监视沟槽（16）（3）的入口和出口槽（14,15）从所述顶表面之间延伸（4）单块体（2）到respectivement掩埋沟道（3） ， 实时PCR监测是通过窜光束到掩埋信道（3），由此，光束照射在其中的流体，并通过收集和处理光束从监视沟槽出来（16）中进行，并发射的由 掩埋通道内的流体（3）。

公开(公告)号：EP1719993A1

公开(公告)日：2006-11-08

申请号：EP05425306.7

申请日：2005-05-06

Applicant: STMicroelectronics S.r.l.

Inventor： Villa, Flavio Francesco ,  Corona, Pietro ,  Barlocchi, Gabriele ,  Baldo, Lorenzo

IPC: G01L7/08 ,  G01L9/00

CPC classification number: G01L9/0045 ,  G01L13/025

Abstract: In a process for manufacturing an integrated differential pressure sensor, the steps of: forming, in a monolithic body (30) of semiconductor material having a first face (30a) and a second face (30b), a cavity (36) extending at a distance from the first face (30a) and delimiting therewith a flexible membrane (37); forming an access passage (42; 42, 44), in fluid communication with the cavity (36); and forming, in the flexible membrane (37), at least one transduction element (38, 72) configured so as to convert a deformation of the flexible membrane (37) into electrical signals. The cavity (36) is formed in a position set at a distance from the second face (30b) and delimits, together with the second face (30b), a portion of the monolithic body (30). In order to form the access passage (42; 42, 44), the monolithic body (30) is etched so as to form an access trench (42) extending through it.

Abstract translation: 在制造集成的差压传感器的过程中，包括以下步骤：在具有第一面（30a）和第二面（30b）的半导体材料的整体体（30）中形成在 距离第一面（30a）的距离并且用其限定柔性膜（37）; 形成与所述空腔（36）流体连通的进入通道（42; 42,44）。 以及在所述柔性膜（37）中形成至少一个构造成将所述柔性膜（37）的变形转换成电信号的换能元件（38,72）。 空腔（36）形成在与第二面（30b）相距一定距离的位置，与第二面（30b）一起界定整体式本体（30）的一部分。 为了形成进入通道（42; 42,44），对整体式主体（30）进行蚀刻，以形成延伸穿过其的通道沟槽（42）。

公开(公告)号：EP1684079A1

公开(公告)日：2006-07-26

申请号：EP05425028.7

申请日：2005-01-25

Applicant: STMicroelectronics S.r.l.

Inventor： Combi, Chantal ,  Baldo, Lorenzo ,  Faralli, Dino ,  Villa, Flavio Francesco

IPC: G01P15/12 ,  G01P15/08

CPC classification number: G01P15/123 ,  G01P15/0802 ,  G01P15/18 ,  G01P2015/084

Abstract: A manufacturing process of a semiconductor piezoresistive accelerometer (35) includes the steps of: providing a wafer (11) of semiconductor material; providing a membrane (23) in the wafer (11) over a cavity (22); rigidly coupling an inertial mass (25) to the membrane (23); and providing, in the wafer (11), piezoresistive transduction elements (24), that are sensitive to strains of the membrane (23) and generate corresponding electrical signals. The step of coupling is carried out by forming the inertial mass (25) on top of a surface of the membrane (23) opposite to the cavity (22). The accelerometer (35) is advantageously used in a device for monitoring the pressure (30) of a tyre of a vehicle. The cavity may be formed as a buried cavity. The mass may be formed by silk-screen printing of a metal paste.

Abstract translation: 半导体压阻加速度计（35）的制造工艺包括以下步骤：提供半导体材料的晶片（11）; 在所述晶片（11）上方的空腔（22）上提供膜（23）; 将惯性质量块（25）刚性耦合到膜（23）上; 以及在所述晶片（11）中提供对所述膜（23）的应变敏感的压阻转导元件（24）并产生相应的电信号。 通过在与空腔（22）相对的膜（23）的表面的顶部上形成惯性质量（25）来进行联接的步骤。 加速度计（35）有利地用于监测车辆的轮胎的压力（30）的装置中。 空腔可以形成为掩埋腔。 质量可以通过丝网印刷金属浆料形成。

公开(公告)号：EP1638141A1

公开(公告)日：2006-03-22

申请号：EP04425687.3

申请日：2004-09-16

Applicant: STMicroelectronics S.r.l.

Inventor： Barlocchi, Gabriele ,  Villa, Flavio Francesco

IPC: H01L21/762 ,  H01L21/20 ,  H01L21/324 ,  H01L21/302

CPC classification number: H01L21/3247 ,  H01L21/3043 ,  H01L21/76251 ,  H01L21/76259

Abstract: Process for manufacturing a wafer using semiconductor processing techniques, wherein a bonding layer (11) is formed on a top surface of a first wafer (10); a deep trench (21) is dug in a substrate (W Si 2) of semiconductor material belonging to a second wafer (20); a top layer (22) of semiconductor material is formed on top of the substrate so as to close the deep trench (21) at the top and form at least one buried cavity (24); the top layer (22) of the second wafer (30) is bonded to the first wafer (10) through the bonding layer (11); the two wafers are subjected to a thermal treatment that causes bonding of at least one portion (42) of the top layer (22) to the first wafer (10) and widening of the buried cavity (24). In this way, the portion (42) of the top layer (22) bonded to the first wafer (10) is separated from the rest (60) of the second wafer (30), to form a composite wafer (50).

公开(公告)号：EP1535665A1

公开(公告)日：2005-06-01

申请号：EP03425771.7

申请日：2003-11-28

Applicant: STMicroelectronics S.r.l.

Inventor： Mastromatteo, Ubaldo ,  Villa, Flavio Francesco ,  Barlocchi, Gabriele

IPC: B01L3/00 ,  B81B3/00

CPC classification number: B01L3/502715 ,  B01L3/5025 ,  B01L3/502707 ,  B01L7/52 ,  B01L2200/027 ,  B01L2200/12 ,  B01L2300/044 ,  B01L2300/0816 ,  B01L2300/1827

Abstract: The microreactor (22) is formed by a sandwich including a first body (1), an intermediate sealing layer (20) and a second body (15). A buried channel (3) extends in the first body (1) and communicates with the surface (12) of the first body (1) through a first and a second apertures (14a, 14b). A first and a second reservoirs (16a, 16b) are formed in the second body (15) and are at least partially aligned with the first and second apertures (14a, 14b). The sealing layer (20) separates the first aperture (14a) from the first reservoir (16a) and the second aperture (14b) from the second reservoir (16b), thereby avoiding contamination of liquids contained in the buried channel from the outside and from any adjacent buried channels (3).

Abstract translation: 微反应器（22）通过夹心包括第一主体（1）至中间密封层（20）和第二本体（15）形成。 掩埋通道（3）在所述第一主体（1）延伸，并且通过第一和第二孔与所述第一主体（1）的表面（12）进行通信（14A，14B）。 第一和第二储存器（16A，16B）形成在所述第二主体（15）和至少部分地与所述第一和第二孔对齐的（14A，14B）。 密封层（20）分离从所述第一储存器（16A）的第一孔（14a）和所述第二孔（14b）的从所述第二储存器（16B），从而避免从外部和从在掩埋沟道所含液体污染 相邻的任何埋入通道（3）。