METHOD OF ENCAPSULATING A SEMICONDUCTOR PACKAGE
    12.
    发明申请
    METHOD OF ENCAPSULATING A SEMICONDUCTOR PACKAGE 审中-公开
    封装半导体封装的方法

    公开(公告)号:WO1997033312A1

    公开(公告)日:1997-09-12

    申请号:PCT/US1997003273

    申请日:1997-03-04

    Applicant: TESSERA, INC.

    Abstract: A method of encapsulating a semiconductor device. The encapsulation method includes a semiconductor chip package assembly (10) having a spacer (20) layer between a top surface of a sheet-like substrate (16) and a contact bearing surface of a semiconductor chip (12), wherein the substrate (16) has conductive leads (22) thereon, the leads (22) being electrically connected to terminals (26) on a first end and bonded to respective chip contacts (24) on a second end. Typically, the spacer layer (20) is comprised of a compliant or elastomeric material (40). A protective layer (30) is attached on a bottom surface of the substrate (16) so as to cover the terminals (26) on the substrate. A flowable, curable encapsulant material (40) is deposited around a periphery of the semiconductor chip (12) after the attachment of the protective layer (30) so as to encapsulate the leads (22). The encapsulant material (40) is then cured. Typically, this encapsulation method is performed on a plurality of chip assemblies simultaneously.

    Abstract translation: 一种封装半导体器件的方法。 封装方法包括在片状基片(16)的顶表面和半导体芯片(12)的接触支承表面之间具有间隔层(20)的半导体芯片封装组件(10),其中衬底(16) )在其上具有导电引线(22),引线(22)在第一端上电连接到端子(26)并且在第二端上结合到相应的芯片触点(24)。 通常,间隔层(20)由顺应性或弹性体材料(40)组成。 保护层(30)安装在基板(16)的底表面上,以覆盖基板上的端子(26)。 在保护层(30)的附着之后,围绕半导体芯片(12)的周边沉积可流动的可固化的密封剂材料(40)以封装引线(22)。 密封剂材料(40)然后固化。 通常,这种封装方法同时在多个芯片组件上执行。

    MULTI-LAYER CIRCUIT CONSTRUCTION METHODS AND STRUCTURES WITH CUSTOMIZATION FEATURES AND COMPONENTS FOR USE THEREIN
    14.
    发明申请
    MULTI-LAYER CIRCUIT CONSTRUCTION METHODS AND STRUCTURES WITH CUSTOMIZATION FEATURES AND COMPONENTS FOR USE THEREIN 审中-公开
    多层电路构造方法和结构与自定义特征及组件的使用

    公开(公告)号:WO1993013637A1

    公开(公告)日:1993-07-08

    申请号:PCT/US1992011395

    申请日:1992-12-30

    Applicant: TESSERA, INC.

    Abstract: A multi-layer circuit panel assembly is formed by laminating circuit panels (10) with interposers (12) incorporating flowable conductive material (48) at interconnect locations and a flowable dielectric material (30, 38) at other locations. Excess materials are captured in reservoirs (20) in the circuit panels. The flowable materials and reservoirs allow the interposers to compress and take up tolerances in the components. The stacked panels may have contacts (538) on their top surfaces, through conductors (527) extending between top and bottom and terminals (530) connected to the bottom end of each through conductor. The terminals and contacts are nonselectively connected to one another at each interface so that wherever a terminal and contact an adjacent panels are aligned with one another, these are connected to one another. This forms composite vertical conductors extending through a plurality of the panels. The selective treatment of the panel top and bottom surfaces provides selective interruptions in the vertical conductors.

    Abstract translation: 多层电路板组件通过层叠具有在互连位置处包含可流动导电材料(48)的插入件(12)的电路板(10)和在其它位置处的可流动电介质材料(30,38)形成。 多余的材料被捕获在电路板中的储存器(20)中。 可流动的材料和储存器允许内插器压缩并占据部件中的公差。 堆叠的板可以在其顶表面上具有通过在顶部和底部之间延伸的导体(527)和连接到每个贯通导体的底端的端子(530)之间的触点(538)。 端子和触头在每个接口处彼此非选择性地连接,使得当端子和邻近的面板彼此对准时,它们彼此连接。 这形成延伸穿过多个面板的复合垂直导体。 面板顶部和底部表面的选择性处理在垂直导体中提供选择性的中断。

    MICROELECTRONIC BONDING WITH LEAD MOTION
    18.
    发明申请
    MICROELECTRONIC BONDING WITH LEAD MOTION 审中-公开
    微电子与铅运动结合

    公开(公告)号:WO1996009745A1

    公开(公告)日:1996-03-28

    申请号:PCT/US1995011899

    申请日:1995-09-19

    Applicant: TESSERA, INC.

    Abstract: A method of connecting a semiconductor chip assembly (12) having at least first and second contacts (18) to a connection component (20) including at least first and second connection leads (30) by means of a tool (60) consisting of the steps of juxtaposing moving and connecting the leads to the corresponding contacts. The connection component (20) is juxtaposed with the semiconductor chip assembly (12) so that the first and second connection leads (30) are aligned with the first and second contacts (18) in such a manner that the first connection lead is offset from the first contact in the first direction and the second connection lead is offset from the second contact in the same first direction. The first connection lead is moved by means of the tool (60) substantially downwardly and towards the first contact in a second direction which is opposite to the first direction, so that an open space (A1) is formed between the first connection lead and the second contact and lead to facilitate movement of the second connection lead by the tool (60) substantially downwardly and towards the second contact in the second direction.

    Abstract translation: 一种将具有至少第一和第二触点(18)的半导体芯片组件(12)连接到包括至少第一和第二连接引线(30)的连接部件(20)的方法,所述工具(60)包括: 将引线并排连接到相应的触点的步骤。 连接部件(20)与半导体芯片组件(12)并置,使得第一和第二连接引线(30)与第一和第二触点(18)对准,使得第一连接引线偏离 第一方向上的第一接触和第二连接引线在相同的第一方向上偏离第二接触。 第一连接引线通过工具(60)基本上向下并且沿与第一方向相反的第二方向朝向第一接触件移动,使得在第一连接引线和第二连接引线之间形成开放空间(A1) 并且导致便于工具(60)沿着第二方向大致向下并朝着第二接触件移动第二连接引线。

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