公开(公告)号：KR1020110064514A

公开(公告)日：2011-06-15

申请号：KR1020090121167

申请日：2009-12-08

Applicant: 동국대학교 산학협력단

Inventor： 송민규 ,  김대윤 ,  문준호

IPC: H03M1/12 ,  H03M1/58

CPC classification number: H03M1/56 ,  H03M1/58 ,  H03M2201/192 ,  H03M2201/22 ,  H03M2201/53 ,  H03M2201/61

Abstract: PURPOSE: A nonlinear single slope AD converter, an image sensor device using the same, a temperature sensor device using the same and a nonlinear slope AD conversion method are provided to acquire reliable nonlinear characteristics by using a digital circuit. CONSTITUTION: A ramp generating part generates a ramp input having a set gradient. A comparator(110) compares an input voltage with the ramp input. A control block(120) transfers information about a comparison time point between the input voltage and the ramp input to a memory unit(140). The control block generates the signal saved in the memory unit or the signal for calling information. The nonlinear counter generates a signal with difference sampling frequencies from inputted clock signals.

Abstract translation: 目的：提供一种非线性单斜率AD转换器，使用该单斜率AD转换器的图像传感器装置，使用其的温度传感器装置和非线性斜率AD转换方法，以通过使用数字电路来获得可靠的非线性特性。 构成：斜坡发生部分产生具有设定梯度的斜坡输入。 比较器（110）将输入电压与斜坡输入进行比较。 控制块（120）将关于输入电压和斜坡输入之间的比较时间点的信息传送到存储器单元（140）。 控制块产生保存在存储器单元中的信号或用于呼叫信息的信号。 非线性计数器产生具有来自输入时钟信号的差采样频率的信号。

公开(公告)号：KR1020100119409A

公开(公告)日：2010-11-09

申请号：KR1020090038511

申请日：2009-04-30

Applicant: 주식회사 실리콘웍스

Inventor： 김기덕 ,  조규형 ,  전용준 ,  전진용 ,  정승철 ,  이성우

IPC: H03M1/66 ,  H03M1/12

CPC classification number: H03M1/66 ,  H03M2201/61 ,  H03M2201/62 ,  H03M2201/711 ,  H03M2201/814 ,  H03M2201/932

Abstract: PURPOSE: An apparatus for transferring a reference current is provided to reduce the size of an entire circuit by accurately sampling or holding the reference current regardless of the generation of mismatches in processes. CONSTITUTION: A first switch part(10) includes a first n-type metal oxide semiconductor(NMOS) transistor(11), a second NMOS transistor(13), and a third NMOS transistor(15). The first switch part transfers a reference current from reference current source(Ireft) according to a controlling signal. A sampling or holding part(20) includes a first current storing part(Cn) and a fourth NMOS transistor(21). The sampling or holding part samples or holds the reference current for a pre-set time. A second switch part(30) includes a first inverter(31) and a fifth NMOS transistor(33).

Abstract translation: 目的：提供用于传送参考电流的装置，以便通过精确地采样或保持参考电流来减小整个电路的尺寸，而不管工艺中产生不匹配。 构成：第一开关部件（10）包括第一n型金属氧化物半导体（NMOS）晶体管（11），第二NMOS晶体管（13）和第三NMOS晶体管（15）。 第一开关部分根据控制信号从参考电流源（Ireft）传送参考电流。 采样或保持部分（20）包括第一电流存储部分（Cn）和第四NMOS晶体管（21）。 采样或保持部分采样或保持参考电流达预设时间。 第二开关部分（30）包括第一反相器（31）和第五NMOS晶体管（33）。

公开(公告)号：KR20100085322A

公开(公告)日：2010-07-29

申请号：KR20090004534

申请日：2009-01-20

Applicant: IUCF HYU

Inventor： YOO CHANG SIK ,  JO JUN GI ,  CHOI WOO SEOK

IPC: H03M3/02

CPC classification number: H03M3/39 ,  H01L27/0922 ,  H03M2201/61 ,  H03M2201/64

Abstract: PURPOSE: The continuous-time sigma-delta modulator can reduce the burden which has to increase the peak value of on current by being proceed the charging operation or the electric discharge operation with the capacitors of 2 through one cycle whole. CONSTITUTION: An integrator(200) integrates the difference of the analog signal and the differential-inputted input signal. The analog to digital convertor(220) changes the output of integrator into the digital output signal. The digital analog converter(240) changes the digital output signal into the analog signal. In the first switching route is the discharge section, the analog signal corresponding to the digital output signal is generated. In the first switching route is the filled sphere liver, the reference voltage is stored.

Abstract translation: 目的：连续时间Σ-Δ调制器可以减少负载，通过进行充电操作或放电操作，电容器2通过一个周期整体，增加电流峰值。 构成：积分器（200）集成了模拟信号和差分输入信号的差异。 模数转换器（220）将积分器的输出变为数字输出信号。 数字模拟转换器（240）将数字输出信号改变成模拟信号。 在第一开关路径中为放电部，产生与数字输出信号对应的模拟信号。 在第一个切换路线是充满球体的肝脏，参考电压被存储。

公开(公告)号：KR1020070017048A

公开(公告)日：2007-02-08

申请号：KR1020060073630

申请日：2006-08-04

Applicant: 산요덴키가부시키가이샤

Inventor： 오니시아끼노부

IPC: H03M1/12 ,  H03H19/00

CPC classification number: H03M3/356 ,  H03H19/00 ,  H03M3/43 ,  H03M3/456 ,  H03M2201/61 ,  H03M2201/622

Abstract: 적분기의 적분 정밀도 및 Δ∑ 변조 회로의 변조 정밀도를 향상시켜, Δ∑ 변조형 AD 컨버터에서의 왜율 열화를 억제한다. 제1∼제4 스위치를 갖는 스위치드 캐패시터를 이용하여 구성되는 적분기의 상기 제2 및 제3 스위치와, 상기 제1 및 제4 스위치를 상보적으로 온오프하는 스위치 제어 회로로서, 상기 제1 및 제4 스위치를 오프 상태, 상기 제2 및 제3 스위치를 온 상태로 할 때에는, 상기 제4 스위치를 오프 상태로 하기 전에, 상기 제2 스위치를 온 상태로 한다.
오디오 기기, Δ∑ 변조 회로, AD 컨버터, 적분기, 양자화기

公开(公告)号：KR1020010074152A

公开(公告)日：2001-08-04

申请号：KR1020010017489

申请日：2001-04-02

Applicant: 최증목

Inventor： 최증목

IPC: H03M1/36

CPC classification number: H03M1/38 ,  H03M2201/61

Abstract: PURPOSE: An analog/digital converter is provided to output analog/digital signal by carrying out circulation with returning the signal voltage, which passed the circuits, to a subtracting machine and thereby the fast speed is maintained and the resolution accuracy is improved. CONSTITUTION: The analog/digital converter includes a multi- level comparator and a linear priority encoder etc. When the analog voltage is permitted to the subtracting machine, the output of the subtracting machine is evenly distributed to the multi-level comparator. Each comparator compares the output with the reference voltage and the L functional value is output. When the functional value data passes through the linear priority encoder and is stored temporarily, it is reversed into the H functional value and is output and then it return to the subtracting machine. The linear priority encoder outputs the L functional value to the priority bit through the low-ranking bit from high-ranking bit. If the output of the comparator to be compared is Vout

Abstract translation: 目的：提供模拟/数字转换器，通过使通过电路的信号电压返回到减法机进行循环来输出模拟/数字信号，从而保持快速并提高分辨率。 构成：模拟/数字转换器包括多电平比较器和线性优先级编码器等。当允许模拟电压到减法器时，减法器的输出均匀分布到多电平比较器。 每个比较器将输出与参考电压进行比较，并输出L功能值。 当功能值数据通过线性优先级编码器并临时存储时，将其反转为H功能值，并输出，然后返回减法机。 线性优先级编码器通过来自高位的低位比特将L功能值输出到优先级位。 如果要比较的比较器的输出为Vout

公开(公告)号：KR1020150072972A

公开(公告)日：2015-06-30

申请号：KR1020130160711

申请日：2013-12-20

Applicant: 한국과학기술원

Inventor： 류승탁 ,  김종인 ,  민기정

IPC: H03M1/12

CPC classification number: H03M1/1009 ,  H03M1/002 ,  H03M1/202 ,  H03M2201/61 ,  H03M2201/6309 ,  H03M2201/718

Abstract: 복수개의제 1 래치를구비하고, 각제 1 래치는상기아날로그신호에대응되는아날로그입력전압및 각기준전압을입력받고제 1 클록에따라두 전압차이를증폭하여제 1 차동 (+)출력과제 1 차동 (-)출력을출력하는제 1 래치단; 복수개의제 2 래치를구비하고, 하나의제 1 래치의차동출력을각각 (+),(-)입력단으로입력받고제 2 클록에따라두 전압차이를증폭하여제 2 차동 (+)출력과 (-)출력을출력하는제 2 래치및 어느하나의제 1 래치의제 1 차동 (-)출력과상기제 1 래치의기준전압과인접한낮은기준전압을수신하는인접제 1 래치의제 1 차동 (+)출력을각각 (+),(-)단자로입력받고제 2 클록에따라두 전압차이를증폭하여제 2 차동 (+)출력과 (-)출력을출력하는제 2 래치를포함하는제 2 래치단; 어느하나의제 2 래치의 (-)출력값과상기어느하나의제 2 래치의인접한하위제 2 래치의 (+)출력값을수신하여 High신호또는 Low신호의인터폴레이션출력을생성하는제 3 SR 래치를포함하는제 3 SR 래치단; 및상기제 3 SR 래치에대응되는아날로그입력전압이상기제 1 래치에입력되면상기제 3 SR 래치의출력을수신하여상기출력이상기 Low신호인경우에는상기제 1 클록에대비하여상기제 2 클록의지연시간이짧아지고상기출력이상기 High신호인경우에는상기제 1 클록에대비하여상기제 2 클록의지연시간이길어지도록조절하는제 2 클록조절회로부를포함하는클록캘리브레이션장치를제공한다.

Abstract translation: 提供了一种时钟校准装置，包括：具有多个第一锁存器的第一锁存端，接收与模拟信号和标准电压相对应的模拟输入电压，根据第一时钟放大电压之间的不同，并输出第一 差分（+）输出和第一差分（ - ）输出; 第二锁存端具有多个第二锁存器，并且包括第二锁存器，其接收通过（+）和（ - ）输入端的第一锁存器的差分输出，并通过放大一个输出端输出第二差分（+）输出和（ - ）输出 根据第二时钟的电压之间的差异，并且还包括接收第一锁存器的第一差分（ - ）输出的第二锁存器和相邻的第一锁存器的第一差分（+）输出，其接收与标准相邻的较低标准电压 分别通过（+）和（ - ）结束第一电压的电压，并且通过根据第二时钟放大不同的电压来输出第二（+）输出和（ - ）输出; 第三SR锁存器端包括接收第二锁存器的（ - ）输出值的第三SR锁存器和与第二锁存器相邻的下部第二锁存器的（+）输出值，并产生高信号或低电平的内插输出 信号; 以及第二时钟调整电路单元，当与所述第三SR锁存器相对应的模拟输入电压被输入到所述第一锁存器时，所述第二时钟调节电路单元接收所述第三SR锁存器的输出，其中当所述第一时钟的输出 是低信号，并且当输出为高信号时，与第一时钟相比，第二时钟的延迟时间变长。

公开(公告)号：KR1020140120407A

公开(公告)日：2014-10-14

申请号：KR1020130035585

申请日：2013-04-02

Applicant: 한양대학교 산학협력단

Inventor： 권오경

IPC: H03M3/02

CPC classification number: H03M3/32 ,  H03M3/39 ,  H03M2201/61 ,  H03M2201/932

Abstract: 더블 샘플링시 발생되는 전력소모를 최소화하기 위한 델타-시그마 변조기가 개시된다. 아날로그 신호는 처리과정을 통해 디지털 신호로 출력되며, 적응형 전류 조절부는 적분기들의 동작에 필요한 소모전력을 결정한다. 이를 위해 적분기의 파형상 출력의 변화가 가장 큰 구간에서 최대 전류가 공급되고, 나머지 구간에서는 공급 전류를 카운팅 동작에 따라 서서히 감소시키게 된다.

Abstract translation: 公开了一种Δ-Σ调制器，以最小化双重采样中产生的功耗。 执行处理过程以输出具有数字信号的模拟信号。 自适应电流控制部分确定积分器的操作所需的功耗。 为此，在积分器的波形输出具有最大变化的范围内提供最大电流。 电源电流根据剩余范围内的计数操作而逐渐减小。

公开(公告)号：KR1020140014455A

公开(公告)日：2014-02-06

申请号：KR1020120080420

申请日：2012-07-24

Applicant: 주식회사 레이믹스

Inventor： 정성재 ,  이정은 ,  김진화 ,  이주호

IPC: H03M3/02

CPC classification number: H03M3/458 ,  H03M3/39 ,  H03M2201/61 ,  H03M2201/932

Abstract: A continuous time sigma-delta analog to digital converter according to a desired embodiment of the present invention includes: a loop filter which has one or more amplifiers; a quantization unit for quantizing signals from the loop filter; a signal detection unit for detecting signals from the quantization unit; and a loop filter stabilization unit for receiving signals from the signal detection unit and adjusting an output of the loop filter. According to the continuous time sigma-delta analog to digital converter to a desired embodiment of the present invention, the continuous time sigma-delta analog to digital converter showing stable circuit operation characteristics without causing oscillations even though a signal which exceeds a predetermined intensity instantaneously, is inputted as an input of the continuous time sigma-delta analog to digital converter by detecting a peak signal of an output stage of the converter and controlling an output of the loop filter can be provided. [Reference numerals] (20) Loop filter; (30) Quantization unit; (60) Signal detection unit; (70) Loop filter stabilization unit

Abstract translation: 根据本发明的期望实施例的连续时间Σ-Δ模数转换器包括：具有一个或多个放大器的环路滤波器; 用于量化来自环路滤波器的信号的量化单元; 信号检测单元，用于检测来自量化单元的信号; 以及环路滤波器稳定单元，用于从信号检测单元接收信号并调整环路滤波器的输出。 根据本发明所需实施例的连续时间Σ-Δ模数转换器，连续时间Σ-Δ模数转换器即使超过预定强度的信号瞬时显示稳定的电路操作特性而不引起振荡， 通过检测转换器的输出级的峰值信号并且可以提供控制环路滤波器的输出，作为连续时间Σ-Δ模数转换器的输入被输入。 （附图标记）（20）环路滤波器; （30）量化单位; （60）信号检测单元; （70）环路滤波器稳定单元

公开(公告)号：KR1020130110557A

公开(公告)日：2013-10-10

申请号：KR1020120032598

申请日：2012-03-29

Applicant: 주식회사 팝코아테크 ,  김남걸

Inventor： 김남걸

IPC: H03M3/02 ,  H03M1/66

CPC classification number: H03M1/66 ,  H03M3/30 ,  H03M2201/61 ,  H03M2201/8152

Abstract: PURPOSE: A digital-analog converter for a multi-bit sigma-delta modulator is provided to enable the multi-bit sigma-delta modulator to process an output signal including a lot of bits and include resolution. CONSTITUTION: A digital-analog converter for a multi-bit sigma-delta modulator includes a positive polarity unit (110), a negative polarity unit (120), and a differential amplifier (130). The positive polarity unit outputs a positive polarity reference voltage according to the output signal of a digital filter. The negative polarity unit outputs a negative polarity reference voltage according to the output signal. The differential amplifier receives the positive polarity reference voltage and the negative polarity reference voltage and outputs a positive polarity voltage and a negative polarity voltage.

Abstract translation: 目的：提供用于多位Σ-Δ调制器的数模转换器，以使多位Σ-Δ调制器能够处理包括大量位的输出信号并包括分辨率。 构成：用于多位Σ-Δ调制器的数模转换器包括正极性单元（110），负极性单元（120）和差分放大器（130）。 正极性单元根据数字滤波器的输出信号输出正极参考电压。 负极性单元根据输出信号输出负极性参考电压。 差分放大器接收正极参考电压和负极性参考电压，并输出正极性电压和负极性电压。

公开(公告)号：KR1020090062271A

公开(公告)日：2009-06-17

申请号：KR1020070129413

申请日：2007-12-12

Applicant: 한국전자통신연구원

Inventor： 박봉혁 ,  이승식 ,  최상성 ,  김석기 ,  김윤정

IPC: H03M1/12

CPC classification number: H03M1/361 ,  H03M1/1205 ,  H03M2201/11 ,  H03M2201/61 ,  H03M2201/718 ,  H03M2201/8132

Abstract: A latch and an analog to digital converter are provided to perform a high speed operation by sensing a current and a voltage in the latch at the same time. A latch includes first to tenth transistor and an inverter(141,142). A first step of the first transistor is connected to a first power source to supply the first power and responds to a reference clock. The second transistor is connected a first node forming a first input terminal. The first step of the second transistor is connected to the second step of the first transistor. A control terminal of the third transistor is connected to a second node forming a second input terminal. The first step of the third transistor is connected to the second step of the first transistor. The control terminal of the fourth transistor is connected to the third node forming the first output terminal and the first step of the fourth transistor is connected to the second node. The second step of the fourth transistor is connected to the fourth node forming the second output terminal. The control terminal of the fifth transistor is connected to the fourth node. The first step of the fifth transistor is connected to the first node and the second step of the fifth transistor is connected to the third node.

Abstract translation: 提供锁存器和模数转换器以通过同时检测锁存器中的电流和电压来执行高速操作。 闩锁包括第一至第十晶体管和反相器（141,142）。 第一晶体管的第一步骤连接到第一电源以提供第一功率并响应参考时钟。 第二晶体管连接形成第一输入端的第一节点。 第二晶体管的第一级连接到第一晶体管的第二级。 第三晶体管的控制端子连接到形成第二输入端子的第二节点。 第三晶体管的第一级连接到第一晶体管的第二级。 第四晶体管的控制端子连接到形成第一输出端子的第三节点，第四晶体管的第一步骤连接到第二节点。 第四晶体管的第二步连接到形成第二输出端的第四节点。 第五晶体管的控制端子连接到第四节点。 第五晶体管的第一级连接到第一节点，第五晶体管的第二级连接到第三节点。