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公开(公告)号：KR1020100119409A
公开(公告)日：2010-11-09
申请号：KR1020090038511
申请日：2009-04-30
Applicant: 주식회사 실리콘웍스
CPC classification number: H03M1/66 , H03M2201/61 , H03M2201/62 , H03M2201/711 , H03M2201/814 , H03M2201/932
Abstract: PURPOSE: An apparatus for transferring a reference current is provided to reduce the size of an entire circuit by accurately sampling or holding the reference current regardless of the generation of mismatches in processes. CONSTITUTION: A first switch part(10) includes a first n-type metal oxide semiconductor(NMOS) transistor(11), a second NMOS transistor(13), and a third NMOS transistor(15). The first switch part transfers a reference current from reference current source(Ireft) according to a controlling signal. A sampling or holding part(20) includes a first current storing part(Cn) and a fourth NMOS transistor(21). The sampling or holding part samples or holds the reference current for a pre-set time. A second switch part(30) includes a first inverter(31) and a fifth NMOS transistor(33).
Abstract translation: 目的：提供用于传送参考电流的装置，以便通过精确地采样或保持参考电流来减小整个电路的尺寸，而不管工艺中产生不匹配。 构成：第一开关部件（10）包括第一n型金属氧化物半导体（NMOS）晶体管（11），第二NMOS晶体管（13）和第三NMOS晶体管（15）。 第一开关部分根据控制信号从参考电流源（Ireft）传送参考电流。 采样或保持部分（20）包括第一电流存储部分（Cn）和第四NMOS晶体管（21）。 采样或保持部分采样或保持参考电流达预设时间。 第二开关部分（30）包括第一反相器（31）和第五NMOS晶体管（33）。
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公开(公告)号：KR1020090045774A
公开(公告)日：2009-05-08
申请号：KR1020070111760
申请日：2007-11-02
Applicant: 에스케이하이닉스 주식회사
CPC classification number: H03M1/68 , H03M1/002 , H03M2201/6107 , H03M2201/62
Abstract: 본 발명은 디지털-아날로그 변환기에서 입력되는 디지털 신호의 비트 수에 따라 증가하는 디지털-아날로그 변환기의 전체 면적을 줄이고 정확도를 높이는 내부 구성과 방법을 제공한다. 이를 위해 본 발명에 따른 디지털-아날로그 변환기는 N(N은 자연수) 비트의 디지털 신호를 입력받아 하위 비트부터 상위 비트를 순서대로 M(M은 자연수) 개의 그룹으로 분류한 뒤 각각의 그룹의 디지털 신호에 가중치를 적용하여 대응하는 아날로그 값을 생성하고 M개의 하위부터 상위 그룹에서 출력된 각각의 아날로그 값을 순서대로 2
(N/M)*0 , 2
(N/M)*1 , ..., 2
(N/M)*(M-1) 배만큼 증가시켜 출력하기 위한 변환 회로를 포함한다. 따라서, 본 발명은 입력되는 디지털 신호의 비트 수에 따라 디지털-아날로그 변환기의 전체 면적이 기하급수적으로 증가하는 것을 막아 고해상도 전자 장치 및 시스템에 적용이 가능하면서 동시에 작은 면적을 가질 수 있다.
이진 가중치 기법, 디지털-아날로그 변환기, 미세 조정, 어림 조정, 칩 면적-
公开(公告)号：KR1020070070992A
公开(公告)日：2007-07-04
申请号：KR1020050134090
申请日：2005-12-29
Applicant: 매그나칩 반도체 유한회사
Inventor： 권종혁
CPC classification number: H03M1/662 , G09G3/36 , H03M2201/62 , H03M2201/814 , H03M2201/932
Abstract: A DAC of a small-sized TFT(Thin Film Transistor) driver IC is provided to reduce a overall size by decreasing a size of a DAC component corresponding to a single channel. A DAC(Digital to Analog Converter) driving circuit for a small-sized display device includes first to third switching elements. The first switching element includes PMOS(Positive Metal Oxide Semiconductor) and NMOS transistors, which are selectively switched by plural first input voltages. The second switching element includes one of the PMOS and NMOS(Negative Metal Oxide Semiconductor) transistors, so that plural second input voltages are selectively switched. The third switching element includes the PMOS and NMOS transistors and selectively switches plural third input voltages.
Abstract translation: 提供小尺寸TFT（薄膜晶体管）驱动器IC的DAC，通过减小对应于单个通道的DAC组件的尺寸来减小总体尺寸。 用于小尺寸显示装置的DAC（数模转换器）驱动电路包括第一至第三开关元件。 第一开关元件包括由多个第一输入电压选择性地切换的PMOS（正金属氧化物半导体）和NMOS晶体管。 第二开关元件包括PMOS和NMOS（负金属氧化物半导体）晶体管之一，从而选择性地切换多个第二输入电压。 第三开关元件包括PMOS和NMOS晶体管，并选择性地切换多个第三输入电压。
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公开(公告)号：KR1020070030002A
公开(公告)日：2007-03-15
申请号：KR1020050084721
申请日：2005-09-12
Applicant: 엘지전자 주식회사
Inventor： 도형욱
CPC classification number: H03M1/36 , H03M1/1205 , H03M2201/2216 , H03M2201/62
Abstract: A high efficiency analog-digital converter is provided to reduce a size of the whole chip in the converter by reducing the number of capacitor arrays which perform a bit conversion by charging a voltage in the analog-digital converter. A high efficiency analog-digital converter includes a charging/discharging circuit, a voltage recording circuit(10), and a voltage switch circuit(SR1,SR2,SR3). The charging/discharging circuit has five capacitors and five charge switches which are connected to an input terminal of a comparator(COM2) in parallel. The voltage recording circuit(10) stores a voltage charged in the charging/discharging circuit every upper four bit and lower four bit. The voltage switch circuit(SR1,SR2,SR3) performs switching for bit conversion of the upper four bit and the lower four bit.
Abstract translation: 提供了一种高效率模数转换器，通过减少通过对模拟数字转换器中的电压进行充电来执行位转换的电容器阵列的数量来减小转换器中整个芯片的尺寸。 高效率模拟数字转换器包括充电/放电电路，电压记录电路（10）和电压开关电路（SR1，SR2，SR3）。 充电/放电电路具有并联连接到比较器（COM2）的输入端的五个电容器和五个充电开关。 电压记录电路（10）存储充电/放电电路中每4位高4位的电压。 电压开关电路（SR1，SR2，SR3）执行上四位和下四位的位转换的切换。
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公开(公告)号：KR1020060079379A
公开(公告)日：2006-07-06
申请号：KR1020040117528
申请日：2004-12-30
Applicant: 동부일렉트로닉스 주식회사
Inventor： 이영성
CPC classification number: H03M1/0609 , H03M1/1009 , H03M1/66 , H03M2201/62 , H03M2201/93
Abstract: 재생 가능한 디지털 아날로그 변환기가 개시된다. 본 발명에 따른 디지털 아날로그 변환기는 디지털 아날로그 변환기 출력의 정밀 제어를 위하여 비교 증폭기를 구비한 기준 셀(reference cell), 기준 셀에서 출력되는 연산값과 대비하여 신호변환을 수행하는 디지털 아날로그 변환기 서브 셀(sub cell), 및 디지털 아날로그 변환기 서브 셀의 전원라인(power line) 사이에 삽입되어 저항값을 보정할 수 있는 저항 보정 회로로 구성된다. 전원라인 사이에 삽입되는 저항 보정 회로는, 하층에 다수인 N개의 배선이 병렬로 형성되어 있는 금속배선들, 및 하층의 금속배선들과 상층의 전원라인을 전기적으로 연결하는 콘택플러그들을 포함하여 최대값 밸런스 불량(full scale balance fail)이 발생한 경우에 n개의 금속배선을 잘라서 n/N(Nn)의 비율로 저항을 상승시켜 칩을 재생시킬 수 있다.
디지털 아날로그 변환기, 최대값 밸런스, 기준 셀, 저항 보정 회로-
Patent Agency Ranking
公开(公告)号：KR1020010055300A
公开(公告)日：2001-07-04
申请号：KR1019990056481
申请日：1999-12-10
Applicant: 에스케이하이닉스 주식회사
Inventor： 홍병일
IPC: H03M1/12
CPC classification number: H03M1/56 , H03M2201/62 , H03M2201/932
Abstract: PURPOSE: A high speed analog-to-digital converter is provided to convert an analog signal into a digital signal after generating a tooth wave according to an n-bit counted value and detecting the level of the analog signal according to the tooth wave. CONSTITUTION: A clock generator(10) generates a clock signal(CLK) of a predetermined period. An N-bit counter(20) performs an n-bit count operation in response to an output signal(CLK) of the clock generator(10). A tooth wave generator(30) generates a tooth wave in response to the counted value of the N-bit counter(20). An amplifier(40) inversely amplifies an output signal of the tooth wave generator(30) according to a ratio of resistors(60,70). A comparator(50) compares an analog signal(VIN) with the amplified tooth wave as a reference voltage. A latch part(80) latches an output of the N-bit counter(20) and outputs a digital signal(OUT) according to an output of the comparator(50).
Abstract translation: 目的：提供高速模数转换器，根据n位计数值产生齿波后，根据牙齿波形检测模拟信号的电平，将模拟信号转换为数字信号。 构成：时钟发生器（10）产生预定周期的时钟信号（CLK）。 N位计数器（20）响应于时钟发生器（10）的输出信号（CLK）执行n位计数操作。 齿波发生器（30）响应于N位计数器（20）的计数值产生齿波。 放大器（40）根据电阻器（60,70）的比例对齿波发生器（30）的输出信号进行反相放大。 比较器（50）将模拟信号（VIN）与放大的齿波作为参考电压进行比较。 锁存部分（80）锁存N位计数器（20）的输出，并根据比较器（50）的输出输出数字信号（OUT）。
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公开(公告)号：KR1020000027231A
公开(公告)日：2000-05-15
申请号：KR1019980045127
申请日：1998-10-27
Applicant: 에스케이하이닉스 주식회사
Inventor： 김경면
IPC: H03M1/00
CPC classification number: H03M1/002 , H03M1/141 , H03M1/202 , H03M1/366 , H03M2201/6185 , H03M2201/62
Abstract: PURPOSE: A folding interpolation analog-digital converter is provided to process signals in a current mode by using a transistor and a resistor only without changing the conventional reference digital CMOS process. CONSTITUTION: The folding interpolation analog-digital converter of high speed and low electric power comprises a plurality of folding sections (1¯4) for receiving and pre-processing an analog signal (Ain) into folding signals of a sinewave having multi-cross points to output as a pair of positive and negative waves, an interpolation section (5) for outputting extra folding signals having cross points of even intervals from the folding signals generated from the two adjacent folding sections of the folding sections (1¯4), a comparison section (6) for comparing the pair of folding signals of the interpolation section (5) with the reference signal to output a lower-leveled signal, an upper-bit AD converting section (7) for comparing the analog signal (Ain) with the reference signal to output an upper-bit signal, a delayed time error correction section (8) for detecting a delay difference between the lower-bit signal outputted from the comparison section (6) and the output signals of the upper-bit AD converting section (7), and a digital encoder (9) for outputting a digital signal (Dout) encoded by receiving the output signal of the comparison section (6).
Abstract translation: 目的：提供折叠插补模数转换器，通过仅使用晶体管和电阻来处理电流模式下的信号，而不改变传统的参考数字CMOS工艺。 构成：高速和低功率的折叠插补模拟数字转换器包括多个折叠部分（1〜4），用于将模拟信号（Ain）预处理成具有多交叉点的正弦波的折叠信号 作为一对正和负波输出，用于从折叠部分（1〜4）的两个相邻折叠部分产生的折叠信号中输出具有偶数间隔交叉点的额外折叠信号的插值部分（5） 比较部分（6），用于将插值部分（5）的折叠信号对与参考信号进行比较以输出较低级别的信号;高位AD转换部分（7），用于将模拟信号（Ain）与 输出高位信号的参考信号，用于检测从比较部分（6）输出的低位信号与输出信号之间的延迟差的延迟时间误差校正部分（8） e高位AD转换部分（7）和用于输出通过接收比较部分（6）的输出信号编码的数字信号（Dout）的数字编码器（9）。
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公开(公告)号：KR101823435B1
公开(公告)日：2018-01-30
申请号：KR1020170028419
申请日：2017-03-06
Applicant: 충북대학교 산학협력단
IPC: H03M1/44
CPC classification number: H03M1/442 , H03M2201/62 , H03M2201/8152
Abstract: 본발명은연속근사방식아날로그디지털변환기및 변환방법에관한것으로서, 변환기를구성하는 DAC 커패시턴스어레이에포함된복수의커패시터에순차적으로감소하는기준전압을인가함으로써, 커패시터어레이크기를획기적으로감소시켜, 연속근사방식아날로그디지털변환기의소형화를가능케하고, 각커패시터의스위칭에소모되는에너지를절감할수 있게한다.
Abstract translation: 本发明涉及一种逐次逼近模拟 - 数字转换器和转换方法，通过应用在所述多个构成变换器包括在DAC电容阵列中电容器的下降顺序的基准电压，通过大幅降低电容器阵列尺寸，连续 这使得可以减小模数转换器的尺寸，并减少开关电容器所消耗的能量。
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公开(公告)号：KR1020140080900A
公开(公告)日：2014-07-01
申请号：KR1020120149943
申请日：2012-12-20
Applicant: 에스케이하이닉스 주식회사 , 한양대학교 산학협력단
IPC: H03M1/12
CPC classification number: H03M3/342 , H03M1/002 , H03M1/12 , H03M2201/19 , H03M2201/62 , H04N5/378
Abstract: The present invention relates to an analog-to-digital converter (ADC) having a reduced area, while performing a correlated double sampling (CDS) operation. The ADC according to the present invention comprises a comparing unit outputting a result of comparison between a voltage of an input node and a comparison voltage; first to N^th capacitors having one end connected to the input node; and first to (N-1)^th voltage selecting units respectively corresponding to the second to N^th capacitors, and selecting one among a first reference voltage, a second reference voltage, and the comparison voltage and applying the selected voltage to the other end of a corresponding capacitor, wherein, during a first sampling operation, a first signal is sampled to the input node, during a first conversion operation, the first to (N-1)^th voltage selecting units select one among the first reference voltage and the second reference voltage in response to an output from the comparing unit, during a second sampling operation, the first to (N-1)^th voltage selecting units select a reference voltage not selected during the first conversion operation, among the first reference voltage and the second reference voltage, and applies a second signal having a level different from that of the first signal to the input node, and during a second conversion operation, a value sampled to the input node during the second sampling operation is converted into a digital signal.
Abstract translation: 本发明涉及在执行相关双重采样（CDS）操作的同时具有减小的面积的模数转换器（ADC）。 根据本发明的ADC包括输出输入节点的电压和比较电压之间的比较结果的比较单元; 第一至第N电容器，其一端连接到输入节点; 以及分别对应于第二至第N电容器的第一至第（N-1）个电压选择单元，并且从第一参考电压，第二参考电压和比较电压中选择一个，并将选择的电压施加到另一个 其中，在第一采样操作期间，第一信号被采样到输入节点，在第一转换操作期间，第一至第（N-1）第二电压选择单元选择第一参考电压 和第二参考电压，响应于来自比较单元的输出，在第二采样操作期间，第一至第（N-1）第二电压选择单元选择在第一转换操作期间未被选择的参考电压， 电压和第二参考电压，并且将具有与第一信号的电平不同的电平的第二信号施加到输入节点，并且在第二转换操作期间，对输入节点采样的值 在第二采样操作期间被转换为数字信号。
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公开(公告)号：KR1020120065226A
公开(公告)日：2012-06-20
申请号：KR1020110119910
申请日：2011-11-17
Applicant: 엘지디스플레이 주식회사
Inventor： 강형원
IPC: H03M1/38
CPC classification number: H03M1/462 , H03M2201/2291 , H03M2201/62 , H03M2201/64 , H03M2201/83
Abstract: PURPOSE: SAR(Successive Approximation Register) ADC(Analog-Digital Converter) and an analog to digital converting method using the same are provided to maintain an optimized operation speed for resolution by enhancing a response speed of a SAR ADC. CONSTITUTION: A SHA(Sampling/Holding Amplifier)(2) samples and holds an analog voltage inputted from the outside. A comparator(4) outputs a comparison signal according to a comparison result by comparing a level of the held analog voltage and a level of an n bit analog signal. A SAR(Successive Approximation Register) logic circuit(6) successively generates a digital signal from the most significant bit to the least significant bit in response to the comparison signal. A DAC(Digital-Analog Converter)(10) changes the successively outputted digital signal into the n bit analog signal. An output register(8) generates an n bit digital signal by holding digital signals successively outputted from the most significant bit to the least significant bit.
Abstract translation: 目的：提供SAR（逐次逼近寄存器）ADC（模拟数字转换器）和使用其的模数转换方法，以通过提高SAR ADC的响应速度来保持分辨率的优化操作速度。 构成：SHA（取样/保持放大器）（2）采样并保持从外部输入的模拟电压。 比较器（4）通过比较保持的模拟电压的电平和n位模拟信号的电平，根据比较结果输出比较信号。 SAR（连续近似寄存器）逻辑电路（6）响应于比较信号，从最高有效位连续产生数字信号到最低有效位。 DAC（数模转换器）（10）将连续输出的数字信号改变为n位模拟信号。 输出寄存器（8）通过将从最高有效位连续输出的数字信号保持为最低有效位来产生n位数字信号。
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