公开(公告)号：KR1020100119409A

公开(公告)日：2010-11-09

申请号：KR1020090038511

申请日：2009-04-30

Applicant: 주식회사 실리콘웍스

Inventor： 김기덕 ,  조규형 ,  전용준 ,  전진용 ,  정승철 ,  이성우

IPC: H03M1/66 ,  H03M1/12

CPC classification number: H03M1/66 ,  H03M2201/61 ,  H03M2201/62 ,  H03M2201/711 ,  H03M2201/814 ,  H03M2201/932

Abstract: PURPOSE: An apparatus for transferring a reference current is provided to reduce the size of an entire circuit by accurately sampling or holding the reference current regardless of the generation of mismatches in processes. CONSTITUTION: A first switch part(10) includes a first n-type metal oxide semiconductor(NMOS) transistor(11), a second NMOS transistor(13), and a third NMOS transistor(15). The first switch part transfers a reference current from reference current source(Ireft) according to a controlling signal. A sampling or holding part(20) includes a first current storing part(Cn) and a fourth NMOS transistor(21). The sampling or holding part samples or holds the reference current for a pre-set time. A second switch part(30) includes a first inverter(31) and a fifth NMOS transistor(33).

Abstract translation: 目的：提供用于传送参考电流的装置，以便通过精确地采样或保持参考电流来减小整个电路的尺寸，而不管工艺中产生不匹配。 构成：第一开关部件（10）包括第一n型金属氧化物半导体（NMOS）晶体管（11），第二NMOS晶体管（13）和第三NMOS晶体管（15）。 第一开关部分根据控制信号从参考电流源（Ireft）传送参考电流。 采样或保持部分（20）包括第一电流存储部分（Cn）和第四NMOS晶体管（21）。 采样或保持部分采样或保持参考电流达预设时间。 第二开关部分（30）包括第一反相器（31）和第五NMOS晶体管（33）。

公开(公告)号：KR1020070070992A

公开(公告)日：2007-07-04

申请号：KR1020050134090

申请日：2005-12-29

Applicant: 매그나칩 반도체 유한회사

Inventor： 권종혁

IPC: H03M1/66 ,  G09G3/36

CPC classification number: H03M1/662 ,  G09G3/36 ,  H03M2201/62 ,  H03M2201/814 ,  H03M2201/932

Abstract: A DAC of a small-sized TFT(Thin Film Transistor) driver IC is provided to reduce a overall size by decreasing a size of a DAC component corresponding to a single channel. A DAC(Digital to Analog Converter) driving circuit for a small-sized display device includes first to third switching elements. The first switching element includes PMOS(Positive Metal Oxide Semiconductor) and NMOS transistors, which are selectively switched by plural first input voltages. The second switching element includes one of the PMOS and NMOS(Negative Metal Oxide Semiconductor) transistors, so that plural second input voltages are selectively switched. The third switching element includes the PMOS and NMOS transistors and selectively switches plural third input voltages.

Abstract translation: 提供小尺寸TFT（薄膜晶体管）驱动器IC的DAC，通过减小对应于单个通道的DAC组件的尺寸来减小总体尺寸。 用于小尺寸显示装置的DAC（数模转换器）驱动电路包括第一至第三开关元件。 第一开关元件包括由多个第一输入电压选择性地切换的PMOS（正金属氧化物半导体）和NMOS晶体管。 第二开关元件包括PMOS和NMOS（负金属氧化物半导体）晶体管之一，从而选择性地切换多个第二输入电压。 第三开关元件包括PMOS和NMOS晶体管，并选择性地切换多个第三输入电压。

公开(公告)号：KR1020020083629A

公开(公告)日：2002-11-04

申请号：KR1020010023076

申请日：2001-04-27

Applicant: 매그나칩 반도체 유한회사

Inventor： 이은평

IPC: H03M1/66

CPC classification number: H03M1/661 ,  H03M2201/814 ,  H03M2201/932

Abstract: PURPOSE: A dual mode digital/analog converter for tuning finely a red, a green, and a blue signals is provided to tune finely a bright part and a dark part by using a dual mode. CONSTITUTION: A driving switch portions(S0-Sk) are controlled by digital input signals(D0-Dk) of k+1 bits. A reference voltage source portion(VDD) supplies a constant voltage. The first PMOS transistor(P1) and the first NMOS transistor(N1) are connected between the reference voltage source portion(VDD) and a ground terminal(VSS). The second PMOS transistor(P2) and the second NMOS transistor(N2) are connected between the reference voltage source portion(VDD) and a ground terminal(VSS). The first node(N1) is commonly connected with a drain of the first PMOS transistor(P1) and a drain of the first NMOS transistor(N1). The second node(N2) is commonly connected with a drain of the second PMOS transistor(P2) and a drain of the second NMOS transistor(N2). The first to the k-th resistances(R1-Rk) are connected between the driving switch portions(S0-Sk). The first switch portion(SA) is connected with a gate of the first PMOS transistor(P1). The second switch portion(SB) is connected with a gate of the first NMOS transistor(N1). The third switch portion(SC) is connected with a gate of the second PMOS transistor(P2). The fourth switch portion(SD) is connected with a gate of the second NMOS transistor(N2).

Abstract translation: 目的：提供用于微调红，绿和蓝信号的双模数字/模拟转换器，通过使用双模式精细调光亮部分和暗部分。 构成：驱动开关部（S0-Sk）由k + 1位的数字输入信号（D0-Dk）控制。 参考电压源部分（VDD）提供恒定电压。 第一PMOS晶体管（P1）和第一NMOS晶体管（N1）连接在参考电压源部分（VDD）和接地端子（VSS）之间。 第二PMOS晶体管（P2）和第二NMOS晶体管（N2）连接在参考电压源部分（VDD）和接地端子（VSS）之间。 第一节点（N1）与第一PMOS晶体管（P1）的漏极和第一NMOS晶体管（N1）的漏极共同连接。 第二节点（N2）与第二PMOS晶体管（P2）的漏极和第二NMOS晶体管（N2）的漏极共同连接。 第一至第k电阻（R1-Rk）连接在驱动开关部分（S0-Sk）之间。 第一开关部分（SA）与第一PMOS晶体管（P1）的栅极连接。 第二开关部分（SB）与第一NMOS晶体管（N1）的栅极连接。 第三开关部分（SC）与第二PMOS晶体管（P2）的栅极连接。 第四开关部分（SD）与第二NMOS晶体管（N2）的栅极连接。

公开(公告)号：KR1020000042418A

公开(公告)日：2000-07-15

申请号：KR1019980058583

申请日：1998-12-24

Applicant: 에스케이하이닉스 주식회사

Inventor： 배종홍

IPC: H03M1/66

CPC classification number: H03M1/38 ,  H03M2201/814 ,  H03M2201/93

Abstract: PURPOSE: An analog-to-digital converting circuit is provided to optimize an analog-to-digital conversion time. CONSTITUTION: An analog-to-digital converting circuit comprises a plurality of analog switches, which selects and outputs one of voltages(V0.8,V1.4,V2.2,V3.1) in response to a 3-bit SAR input signal(SAR£1:3|) of a 4-bit SAR input signal(SAR£1:4|) from an SAR register and a signal(ST£1:4|) indicating a conversion cycle from a digital-to-analog conversion to an analog-to-digital conversion. In an analog-to-digital converting circuit, a final path is previously determined by use of a value of a previously determined SAR register.

Abstract translation: 目的：提供模数转换电路，以优化模数转换时间。 构成：模数转换电路包括多个模拟开关，其响应于3位SAR输入选择并输出电压（V0.8，V1.4，V2.2，V3.1）中的一个 来自SAR寄存器的4位SAR输入信号（SAR£1：4 |）的信号（SAR£1：3 |）和表示来自数字 - 模拟转换为模数转换。 在模数转换电路中，预先通过使用先前确定的SAR寄存器的值来确定最终路径。

公开(公告)号：KR101879331B1

公开(公告)日：2018-07-18

申请号：KR1020170029313

申请日：2017-03-08

Applicant: 충북대학교 산학협력단

Inventor： 양병도 ,  김태우 ,  우기찬 ,  황선광 ,  김미정

IPC: H03M1/78

CPC classification number: H03M1/785 ,  H03M2201/3168 ,  H03M2201/814

Abstract: 본발명은이중출력용폴디드저항열디지털아날로그변환기에관한것으로서, 동일한저항값을갖는 2개의저항들이제1기준전압(V)과제2기준전압(V) 사이에직렬연결되어있는저항열(R)과, N/2의상위비트를출력하는워드라인디코더(Word line decoder)와, N/2의하위비트를출력하는비트라인디코더(Bit line decoder)와, 워드라인디코더의상위비트에대응하는각 출력단에접속되어스위칭되며, 저항열의해당전압값(V)을출력하는 2개의워드라인스위치(WL-S)와, 비트라인디코더의하위비트에대응하는각 출력단에접속되어스위칭되며, 하위비트에대응하는해당전압값(V)을출력하는 N 개의비트라인스위치(BL-S)와, 워드라인디코더의상위비트에대응하는각 출력단에접속되어스위칭되며, 각라인간이웃전압값(V)을출력하는 N 개의워드라인더미스위치(WL-DS)와, 비트라인디코더의하위비트에대응하는각 출력단에접속되어스위칭되며, 하위비트에대응하는해당이웃전압값(V)을전달하는 N 개의비트라인더미스위치(BL-DS)와, 비트라인스위치(BL-S) 및비트라인더미스위치(BL-DS)가일측단자가접속되고, 자신의출력단이타측단자에접속되는출력버퍼(Output buffer)를포함한다. 본발명에따르면, 고해상도를구현하면서도 R-DAC의스위치개수를최소화함으로써, R-DAC의칩 면적을감소시킬수 있다. 데이터구동부(Data Driver) IC칩면적에대부분은 R-DAC가차지하고있으므로, R-DAC의면적을줄임으로써데이터구동부 IC칩의크기감소및 원가절감을달성할수 있다. 또한, 스위치의수가줄어들면스위치가가지고있는기생저항, 캐패시터가감소해 R-DAC 동작속도가빨라져고속처리가가능하게된다.

公开(公告)号：KR1020110047406A

公开(公告)日：2011-05-09

申请号：KR1020090104020

申请日：2009-10-30

Applicant: 인하대학교 산학협력단

Inventor： 윤광섭 ,  황정진

IPC: H03M3/00 ,  H03M3/04

CPC classification number: H03M3/04 ,  H03M2201/644 ,  H03M2201/814 ,  H03M2201/932

Abstract: PURPOSE: A differential switch circuit using an NAND gate and a source amplifier is provided to reduce the over-drive voltage by reducing a swing width of a digital signal applied to a differential switch. CONSTITUTION: A current generating unit(100) is connected to a first common node(CN1) to receive uniform static current. A differential switch unit(300) is connected to the current generating unit through a first common node, and supplies uniform static current. A switch driving circuit unit(500) includes a first source amplifier(510) connected to a third NMOS transistor, a second source amplifier(530) connected to a fourth NMOS transistor, and a NAND gate connected to the first and second source amplifiers.

Abstract translation: 目的：提供使用NAND门和源极放大器的差分开关电路，通过减小施加到差分开关的数字信号的摆幅来减小过驱动电压。 构成：电流产生单元（100）连接到第一公共节点（CN1）以接收均匀的静态电流。 差动开关单元（300）通过第一公共节点连接到电流发生单元，并提供均匀的静态电流。 开关驱动电路单元（500）包括连接到第三NMOS晶体管的第一源极放大器（510），连接到第四NMOS晶体管的第二源极放大器（530）和连接到第一和第二源极放大器的与非门。

公开(公告)号：KR1020070069288A

公开(公告)日：2007-07-03

申请号：KR1020050131230

申请日：2005-12-28

Applicant: 동부일렉트로닉스 주식회사

Inventor： 김일곤

IPC: H03M7/00 ,  H03M1/12

CPC classification number: H03M7/16 ,  H01L27/0922 ,  H03M2201/814

Abstract: A gray code converting device is provided to be implemented in one chip with an A/D converter by using an inverter and a transmission gate for converting a binary code to a gray code. A gray code converting device includes an input register(110), a bit combining unit(120), and an output register(130). The input register receives 4-bit binary codes. The bit combining unit combines the 4-bit binary codes with one another. The output register outputs the combined signal from the bit combining unit which includes first to third bit combining members. A first binary code is arranged to be a first gray code. The first bit combining member(120a) combines the first and second binary codes to generate a second gray code. The second bit combining member(120b) combines the third and second binary codes to generate a third gray code. The third bit combining member(120c) combines the third and fourth binary codes to generate a fourth gray code.

Abstract translation: 通过使用逆变器和用于将二进制代码转换为灰度代码的传输门，提供了用A / D转换器在一个芯片中实现的灰度代码转换装置。 格雷码转换装置包括输入寄存器（110），位组合单元（120）和输出寄存器（130）。 输入寄存器接收4位二进制代码。 比特组合单元将4位二进制码相互组合。 输出寄存器输出来自位组合单元的组合信号，该组合单元包括第一至第三位组合构件。 第一个二进制代码被设置为第一个灰色代码。 第一位组合部件（120a）组合第一和第二二进制代码以产生第二灰度代码。 第二位组合部件（120b）组合第三和第二二进制代码以产生第三灰度代码。 第三位组合部件（120c）组合第三和第四二进制代码以产生第四灰度代码。

公开(公告)号：KR1020060011520A

公开(公告)日：2006-02-03

申请号：KR1020040060403

申请日：2004-07-30

Applicant: 매그나칩 반도체 유한회사

Inventor： 김정민

IPC: H03M1/76 ,  G09G3/20

CPC classification number: H03M1/668 ,  G09G3/20 ,  H03M1/06 ,  H03M1/76 ,  H03M2201/6107 ,  H03M2201/814 ,  H03M2201/932

Abstract: 본 발명은 오버슈트가 발생하지 않아 고속으로 동작할 수 있는 전류구동 디지털아날로그변환장치를 제공하기 위한 것으로, 이를 위한 본 발명으로 서로 다른 복수의 아날로그전류량을 공급하기 위한 전류공급부; 복수비트의 디지털신호를 입력받아 이에 대응하는 상기 아날로그전류량을 출력하기 위한 제1 디지털아날로그변환부; 반전된 상기 복수의 디지털아날로그신호를 입력받아 상기 제1 디지털아날로그변환부와 상보적으로 구동하여 대응하는 상기 아날로그전류량을 출력하기 위한 제2 디지털아날로그변환부; 상기 제1 디지털아날로그변환부에 접속되어, 상기 제1 디지털아날로그변환부의 출력전류를 미러링하여 아날로그신호를 출력하기 위한 제1 로딩부; 및 상기 제2 디지털아날로그변환부의 출력전류를 공급받아 상기 제1 로딩부에 의해 상기 제1 디지털아날로그변환부에 걸리는 바이어스전압과 실질적으로 동일한 전압이 상기 제2 디지털아날로그변환부에 공급되도록 하기 위한 제2 로딩부를 구비하는 디지털아날로그변환장치를 제공한다.
오버슈트(Over Shoot), 고속동작, 스위칭, 안정화시간(settling time), 로드

公开(公告)号：KR1020010111709A

公开(公告)日：2001-12-20

申请号：KR1020000032342

申请日：2000-06-13

Applicant: 인피니언 테크놀로지스 노쓰 아메리카 코포레이션

Inventor： 자비,투스카이

IPC: H03M1/12

CPC classification number: H03M1/745 ,  H03M1/84 ,  H03M2201/814

Abstract: 본발명은디지털아날로그변환에관한것이다. 본발명의실시예에따르면, 대수적변환특성(400)은순환식(504)의기준전류에출력전류의일부를감산함으로써생성될수 있다.

公开(公告)号：KR1020090087988A

公开(公告)日：2009-08-19

申请号：KR1020080013265

申请日：2008-02-14

Applicant: 이타칩스 주식회사

Inventor： 차형우 ,  서준호

IPC: H03M1/66

CPC classification number: H03M1/66 ,  H03M1/002 ,  H03M2201/814 ,  H03M2201/932

Abstract: A circuit for a low voltage CMOS digital to analog converter is provided to be operated at a low voltage by using transistors less than two between a supply voltage and a ground. A digital signal complementation converting part(610) converts a digital signal into an inverted signal and a non-inverted signal. A weighted value current mirror part(620) includes an input terminal transistor and a plurality of output terminal transistors. A plurality of output terminal transistors generates an output current of a value multiplying a reference current value by a fixed weighted value. A plurality of switch parts includes a first switching transistor and a second switching transistor. The first switching transistor turns on/off a spot between a gate of the output terminal transistor and a gate of the input terminal transistor by the non-inverted digital signal generated in the digital signal complementation converting part. A current to voltage converting part(660) converts the output current into an analog voltage.

Abstract translation: 提供了一种用于低电压CMOS数模转换器的电路，通过在电源电压和地之间使用小于2的晶体管在低电压下工作。 数字信号互补转换部（610）将数字信号转换为反相信号和非反相信号。 加权值电流镜部分（620）包括输入端子晶体管和多个输出端子晶体管。 多个输出端子晶体管产生将参考电流值乘以固定加权值的值的输出电流。 多个开关部件包括第一开关晶体管和第二开关晶体管。 第一开关晶体管通过在数字信号互补转换部分中产生的非反相数字信号，在输出端晶体管的栅极和输入端晶体管的栅极之间导通/截止点。 电流 - 电压转换部分（660）将输出电流转换为模拟电压。