公开(公告)号：US20170056926A1

公开(公告)日：2017-03-02

申请号：US15349223

申请日：2016-11-11

Applicant: Butterfly Network, Inc.

Inventor： Jonathan M. Rothberg ,  Keith G. Fife ,  Tyler S. Ralston ,  Gregory L. Charvat ,  Nevada J. Sanchez

IPC: B06B1/02 ,  G10K9/12 ,  G10K11/18 ,  B81B3/00 ,  B81C1/00

CPC classification number: B06B1/0292 ,  B06B1/02 ,  B81B3/0021 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81B2207/015 ,  B81C1/00158 ,  B81C2201/013 ,  B81C2203/0118 ,  B81C2203/0735 ,  B81C2203/0771 ,  G10K9/12 ,  G10K11/18

Abstract: CMOS Ultrasonic Transducers and processes for making such devices are described. The processes may include forming cavities on a first wafer and bonding the first wafer to a second wafer. The second wafer may be processed to form a membrane for the cavities. Electrical access to the cavities may be provided.

Abstract translation: 描述了CMOS超声波传感器及其制造方法。 所述方法可以包括在第一晶片上形成空腔并将第一晶片接合到第二晶片。 可以处理第二晶片以形成用于空腔的膜。 可以提供对腔的电接入。

公开(公告)号：US20160355392A1

公开(公告)日：2016-12-08

申请号：US15238854

申请日：2016-08-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony K. Stamper ,  John G. Twombly

IPC: B81B3/00 ,  H01H59/00 ,  B81C1/00 ,  G06F17/50

CPC classification number: B81B3/0072 ,  B81B3/0021 ,  B81B2201/01 ,  B81B2201/014 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81B2203/04 ,  B81C1/0015 ,  B81C1/00365 ,  B81C1/00476 ,  B81C1/00619 ,  B81C1/00626 ,  B81C1/00666 ,  B81C2201/0109 ,  B81C2201/013 ,  B81C2201/0167 ,  B81C2201/017 ,  B81C2203/0136 ,  B81C2203/0172 ,  G06F17/5068 ,  G06F17/5072 ,  H01H1/0036 ,  H01H57/00 ,  H01H59/0009 ,  H01H2057/006 ,  H01L41/1136 ,  H01L2924/0002 ,  Y10S438/937 ,  Y10T29/42 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49105 ,  Y10T29/49121 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/5313 ,  H01L2924/00

Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes patterning a wiring layer to form at least one fixed plate and forming a sacrificial material on the wiring layer. The method further includes forming an insulator layer of one or more films over the at least one fixed plate and exposed portions of an underlying substrate to prevent formation of a reaction product between the wiring layer and a sacrificial material. The method further includes forming at least one MEMS beam that is moveable over the at least one fixed plate. The method further includes venting or stripping of the sacrificial material to form at least a first cavity.

公开(公告)号：US20160332865A1

公开(公告)日：2016-11-17

申请号：US15155448

申请日：2016-05-16

Applicant: Foresee Technology Corp.

Inventor： Chien-Chan CHEN ,  Yi-Der LIANG ,  Shiao-Yi LIN ,  Cheng-Kuang YANG

IPC: B81B3/00 ,  H04R19/00 ,  H04R19/04 ,  B81C1/00

CPC classification number: B81B3/0054 ,  B81B2201/0257 ,  B81B2203/0118 ,  B81B2203/0361 ,  B81B2207/015 ,  B81B2207/07 ,  B81C1/00246 ,  B81C2201/013 ,  B81C2201/053 ,  B81C2203/0714 ,  B81C2203/0735 ,  H04R19/005 ,  H04R19/04

Abstract: A support pillar is formed under a movable film for support. The support pillar includes a plurality of first metal micropillars, a base metal connection pillar layer and a first oxide encapsulation layer. The first metal micropillars are formed under the movable film and conductively connected to the movable film via metal connection. The base metal connection pillar layer is formed under the first metal micropillars and conductively connected to the first metal micropillars. The first oxide encapsulation layer fully or partially encapsulates the first metal micropillars to insulate the first metal micropillars from air, and shape the support pillar into a column shape.

Abstract translation: 支撑柱形成在用于支撑的可移动膜下。 支撑柱包括多个第一金属微柱，贱金属连接柱层和第一氧化物封装层。 第一金属微透镜形成在可动膜下方，并通过金属连接导电地连接到可动膜上。 基底金属连接柱层形成在第一金属微柱下面，并与第一金属微柱导电连接。 第一氧化物封装层完全或部分地封装第一金属微柱，以将第一金属微柱与空气绝缘，并将支柱形成柱形。

公开(公告)号：US20160304335A1

公开(公告)日：2016-10-20

申请号：US15098353

申请日：2016-04-14

Applicant: Innovative Micro Technology

Inventor： Benedikt ZEYEN

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/0067 ,  B81B2201/0264 ,  B81B2201/047 ,  B81B2207/115 ,  B81C1/00317 ,  B81C3/001 ,  B81C2201/013 ,  B81C2201/0197 ,  B81C2203/031 ,  H01L24/00 ,  H04R19/02

Abstract: A first ion rich dielectric substrate with a patterned dielectric barrier and a oxidizable metal layer is anodically bonded to a second ion rich dielectric substrate. To bond the substrates, the oxidizable metal layer is oxidized. The dielectric barrier may inhibit the migration of these ions to the bondline, which might otherwise poison the bond strength. Accordingly, when joining the two substrates, a strong bond is maintained between the wafers.

Abstract translation: 具有图案化电介质阻挡层和可氧化金属层的第一富离子电介质基片阳极结合到第二富离子电介质基片上。 为了结合基板，可氧化的金属层被氧化。 电介质阻挡层可以抑制这些离子迁移到粘结线，否则可能会损害粘结强度。 因此，当接合两个基板时，在晶片之间保持牢固的结合。

公开(公告)号：US09434166B2

公开(公告)日：2016-09-06

申请号：US14316487

申请日：2014-06-26

Applicant: STMicroelectronics, Inc.

Inventor： Ming Fang ,  Fuchao Wang

IPC: F24H1/18 ,  F24H1/20 ,  B41J2/05 ,  B41J2/16 ,  B41J2/14

CPC classification number: B81C1/00119 ,  B41J2/14056 ,  B41J2/14072 ,  B41J2/14137 ,  B41J2/16 ,  B41J2/1601 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1639 ,  B81B1/006 ,  B81B2201/052 ,  B81B2201/058 ,  B81C2201/013 ,  B81C2203/075 ,  H01L28/20 ,  Y10T29/41 ,  Y10T29/49401 ,  Y10T29/49826

Abstract: An integrated semiconductor heating assembly includes a semiconductor substrate, a chamber formed therein, and an exit port in fluid communication with the chamber, allowing fluid to exit the chamber in response to heating the chamber. The integrated heating assembly includes a first heating element adjacent the chamber, which can generate heat above a selected threshold and bias fluid in the chamber toward the exit port. A second heating element is positioned adjacent the exit port to generate heat above a selected threshold, facilitating movement of the fluid through the exit port away from the chamber. Addition of the second heating element reduces the amount of heat emitted per heating element and minimizes thickness of a heat absorption material toward an open end of the exit port. Since such material is expensive, this reduces the manufacturing cost and retail price of the assembly while improving efficiency and longevity thereof.

公开(公告)号：US20160244321A1

公开(公告)日：2016-08-25

申请号：US15148130

申请日：2016-05-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Christopher V. JAHNES ,  Anthony K. STAMPER

IPC: B81B3/00 ,  H01H59/00 ,  H01H1/00 ,  B81C1/00

CPC classification number: B81B3/0072 ,  B81B3/0021 ,  B81B2201/01 ,  B81B2201/014 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81B2203/04 ,  B81C1/0015 ,  B81C1/00365 ,  B81C1/00476 ,  B81C1/00619 ,  B81C1/00626 ,  B81C1/00666 ,  B81C2201/0109 ,  B81C2201/013 ,  B81C2201/0167 ,  B81C2201/017 ,  B81C2203/0136 ,  B81C2203/0172 ,  G06F17/5068 ,  G06F17/5072 ,  H01H1/0036 ,  H01H57/00 ,  H01H59/0009 ,  H01H2057/006 ,  H01L41/1136 ,  H01L2924/0002 ,  Y10S438/937 ,  Y10T29/42 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49105 ,  Y10T29/49121 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/5313 ,  H01L2924/00

Abstract: A method of forming a Micro-Electro-Mechanical System (MEMS) includes forming a lower electrode on a first insulator layer within a cavity of the MEMS. The method further includes forming an upper electrode over another insulator material on top of the lower electrode which is at least partially in contact with the lower electrode. The forming of the lower electrode and the upper electrode includes adjusting a metal volume of the lower electrode and the upper electrode to modify beam bending.

Abstract translation: 形成微机电系统（MEMS）的方法包括在MEMS的空腔内的第一绝缘体层上形成下电极。 该方法还包括在下部电极的顶部上形成上部电极，该上部电极至少部分地与下部电极接触。 下电极和上电极的形成包括调节下电极和上电极的金属体积以改变光束弯曲。

公开(公告)号：US20160096721A1

公开(公告)日：2016-04-07

申请号：US14963844

申请日：2015-12-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Christopher V. JAHNES ,  Anthony K. STAMPER

IPC: B81B3/00

CPC classification number: B81B3/0072 ,  B81B3/0021 ,  B81B2201/01 ,  B81B2201/014 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81B2203/04 ,  B81C1/0015 ,  B81C1/00365 ,  B81C1/00476 ,  B81C1/00619 ,  B81C1/00626 ,  B81C1/00666 ,  B81C2201/0109 ,  B81C2201/013 ,  B81C2201/0167 ,  B81C2201/017 ,  B81C2203/0136 ,  B81C2203/0172 ,  G06F17/5068 ,  G06F17/5072 ,  H01H1/0036 ,  H01H57/00 ,  H01H59/0009 ,  H01H2057/006 ,  H01L41/1136 ,  H01L2924/0002 ,  Y10S438/937 ,  Y10T29/42 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49105 ,  Y10T29/49121 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/5313 ,  H01L2924/00

Abstract: A method of forming a Micro-Electro-Mechanical System (MEMS) includes forming a lower electrode on a first insulator layer within a cavity of the MEMS. The method further includes forming an upper electrode over another insulator material on top of the lower electrode which is at least partially in contact with the lower electrode. The forming of the lower electrode and the upper electrode includes adjusting a metal volume of the lower electrode and the upper electrode to modify beam bending.

公开(公告)号：US09260296B2

公开(公告)日：2016-02-16

申请号：US14713269

申请日：2015-05-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Hua Chu ,  Chun-Wen Cheng

IPC: H01L29/82 ,  B81B7/04 ,  B81C1/00 ,  B81B3/00 ,  G01C19/56 ,  G01P15/00 ,  G01L19/00 ,  G01L9/00 ,  G01P15/08 ,  G01P15/125 ,  B81B7/00

CPC classification number: B81C1/00293 ,  B81B3/0021 ,  B81B7/0041 ,  B81B7/007 ,  B81B7/02 ,  B81B7/04 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/025 ,  B81B2201/0264 ,  B81C1/00134 ,  B81C1/00309 ,  B81C2201/013 ,  B81C2203/0118 ,  G01C19/56 ,  G01C19/5769 ,  G01L9/0044 ,  G01L19/0076 ,  G01L19/0092 ,  G01P15/00 ,  G01P15/0802 ,  G01P15/125

Abstract: A method embodiment includes providing a micro-electromechanical (MEMS) wafer including a polysilicon layer having a first and a second portion. A carrier wafer is bonded to a first surface of the MEMS wafer. Bonding the carrier wafer creates a first cavity. A first surface of the first portion of the polysilicon layer is exposed to a pressure level of the first cavity. A cap wafer is bonded to a second surface of the MEMS wafer opposite the first surface of the MEMS wafer. The bonding the cap wafer creates a second cavity comprising the second portion of the polysilicon layer and a third cavity. A second surface of the first portion of the polysilicon layer is exposed to a pressure level of the third cavity. The first cavity or the third cavity is exposed to an ambient environment.

公开(公告)号：US09242854B2

公开(公告)日：2016-01-26

申请号：US14137538

申请日：2013-12-20

Applicant: Intel Corporation

Inventor： Sarah K. Haney ,  Weng Hong Teh ,  Feras Eid ,  Sasha N. Oster

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81B7/0041 ,  B81B7/0032 ,  B81B2203/0315 ,  B81B2207/012 ,  B81B2207/07 ,  B81C1/00293 ,  B81C1/00539 ,  B81C2201/013 ,  B81C2203/0109 ,  B81C2203/0136 ,  B81C2203/0792

Abstract: Embodiments of the invention describe hermetic encapsulation for MEMS devices, and processes to create the hermetic encapsulation structure. Embodiments comprise a MEMS substrate stack that further includes a magnet, a first laminate organic dielectric film, a first hermetic coating disposed over the magnet, a second laminate organic dielectric film disposed on the hermetic coating, a MEMS device layer disposed over the magnet, and a plurality of metal interconnects surrounding the MEMS device layer. A hermetic plate is subsequently bonded to the MEMS substrate stack and disposed over the formed MEMS device layer to at least partially form a hermetically encapsulated cavity surrounding the MEMS device layer. In various embodiments, the hermetically encapsulated cavity is further formed from the first hermetic coating, and at least one of the set of metal interconnects, or a second hermetic coating deposited onto the set of metal interconnects.

Abstract translation: 本发明的实施例描述了用于MEMS器件的气密封装和用于创建气密封装结构的工艺。 实施例包括进一步包括磁体的MEMS基板堆叠，第一层压有机介电膜，设置在磁体上的第一密封涂层，设置在密封涂层上的第二层压有机绝缘膜，设置在磁体上的MEMS器件层，以及 围绕MEMS器件层的多个金属互连。 密封板随后结合到MEMS衬底叠层并且设置在所形成的MEMS器件层上，以至少部分地形成围绕MEMS器件层的气密封装的腔体。 在各种实施例中，气密封装的空腔进一步由第一密封涂层形成，并且该组金属互连中的至少一个或沉积在该组金属互连件上的第二密封涂层。

公开(公告)号：US20150210541A1

公开(公告)日：2015-07-30

申请号：US14504953

申请日：2014-10-02

Applicant: Yu-Fu Kang ,  Chiung-Cheng Lo

Inventor： Yu-Fu Kang ,  Chiung-Cheng Lo

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00285 ,  B81B7/0038 ,  B81B7/02 ,  B81B2207/015 ,  B81C2201/013 ,  B81C2201/019 ,  B81C2203/0792

Abstract: A MEMS chip includes a cap layer and a composite device layer. The cap layer includes a substrate. The substrate has a first region and a second region, wherein the first region includes plural first trenches and the second region has plural second trenches. The first region has a first etch pattern density and the second region has a second etch pattern density, wherein the first etch pattern density is higher than the second etch pattern density to form chambers of different pressures.

Abstract translation: MEMS芯片包括盖层和复合器件层。 盖层包括基底。 衬底具有第一区域和第二区域，其中第一区域包括多个第一沟槽，而第二区域具有多个第二沟槽。 第一区域具有第一蚀刻图案密度，第二区域具有第二蚀刻图案密度，其中第一蚀刻图案密度高于第二蚀刻图案密度以形成不同压力的室。