公开(公告)号：US06467879B1

公开(公告)日：2002-10-22

申请号：US09687096

申请日：2000-10-16

Applicant: Joel A. Kubby ,  Elliott A. Eklund ,  Peter M. Gulvin

Inventor： Joel A. Kubby ,  Elliott A. Eklund ,  Peter M. Gulvin

IPC: B41J204

CPC classification number: F04B43/043 ,  B41J2/14314 ,  B81B3/0051 ,  B81B2201/036 ,  B81B2201/045 ,  B81B2201/052 ,  B81B2203/0127 ,  B81B2203/053

Abstract: A micro-electromechanical fluid ejector having an inner structure on the bottom of the top of the membrane for isolating the conductor, and an outer structure, away from the center of the membrane, on the bottom of the top of the membrane to stop excessive flexing of the membrane leading to inter-electrode contact.

Abstract translation: 微机电流体喷射器，其在膜的顶部底部具有用于隔离导体的内部结构，以及远离膜的中心的外部结构，位于膜的顶部的底部以阻止过度弯曲 的膜导致电极间接触。

公开(公告)号：US20020096488A1

公开(公告)日：2002-07-25

申请号：US09768688

申请日：2001-01-24

Applicant: Xerox Corporation

Inventor： Peter M. Gulvin ,  Elliott A. Eklund

IPC: G11B005/127 ,  B41J002/04

CPC classification number: B81B3/007 ,  B41J2/14314 ,  B41J2/16 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1631 ,  B41J2/1639 ,  B41J2/1642 ,  B81B2201/052 ,  B81B2203/0127 ,  F04B43/043 ,  H04R7/08

Abstract: A method for fabricating a membrane having a corrugated, multi-layer structure, comprising the steps of: providing a substrate having an insulator layer on the top surface of the substrate, a conductive layer on the insulator layer, a sacrificial layer on said conductive layer, and a second conductive layer; patterning a series of holes the second conductive layer to allow release etchant to have access to a second sacrificial layer; depositing the second sacrificial layer onto said second conductive layer so that the series of holes are filled with the second sacrificial layer; patterning the second sacrificial layer with a radial and/or concentric grid pattern so that a third conductive layer when deposited will form the support structure and top portion of the corrugated structure; depositing the third conductive layer so that the grid pattern is filled in and is in contact with the second conductive layer; removing the first and second sacrificial layer by immersing the device in a release etchant.

Abstract translation: 一种用于制造具有波纹状多层结构的膜的方法，包括以下步骤：在所述基板的顶表面上提供具有绝缘体层的基板，所述绝缘体层上的导电层，所述导电层上的牺牲层 ，和第二导电层; 将一系列孔图案化成第二导电层，以允许剥离蚀刻剂进入第二牺牲层; 将所述第二牺牲层沉积到所述第二导电层上，使得所述一系列孔被所述第二牺牲层填充; 以径向和/或同心网格图案图案化第二牺牲层，使得沉积时的第三导电层将形成波纹结构的支撑结构和顶部; 沉积第三导电层，使得栅格图案被填充并与第二导电层接触; 通过将设备浸入释放蚀刻剂中来去除第一和第二牺牲层。

公开(公告)号：US06291317B1

公开(公告)日：2001-09-18

申请号：US09730819

申请日：2000-12-06

Applicant: Nicholas J. Salatino ,  John C. Ackerman

Inventor： Nicholas J. Salatino ,  John C. Ackerman

IPC: H01L2146

CPC classification number: B81C1/00888 ,  B81B2201/052 ,  Y10S83/906 ,  Y10S83/945 ,  Y10T83/0524 ,  Y10T83/0572 ,  Y10T83/0581 ,  Y10T83/0586

Abstract: A method for dicing small devices including MEMS, ink jet printheads, lasers etc. The method comprises making a first pass cut into a substrate with a blade of narrow kerf and having long wear characteristics. This first pass cut is then followed with a polishing blade of wider kerf having desirable smooth cutting qualities.

Abstract translation: 一种用于切割小型器件（包括MEMS，喷墨打印头，激光器等）的方法。该方法包括使用具有窄切口刀片并具有长磨损特性的第一次通过切割成基底。 然后，第一次通过切割随后具有较宽切口的抛光刀片具有所需的平滑切割质量。

公开(公告)号：US6143190A

公开(公告)日：2000-11-07

申请号：US967732

申请日：1997-11-12

Applicant: Takayuki Yagi ,  Junichi Kobayashi ,  Yasushi Kawasumi ,  Genzo Momma ,  Kenji Makino ,  Kei Fujita ,  Yasushi Matsuno ,  Yukihiro Hayakawa ,  Masahiro Takizawa

Inventor： Takayuki Yagi ,  Junichi Kobayashi ,  Yasushi Kawasumi ,  Genzo Momma ,  Kenji Makino ,  Kei Fujita ,  Yasushi Matsuno ,  Yukihiro Hayakawa ,  Masahiro Takizawa

IPC: B41J2/05 ,  B41J2/16 ,  B81B3/00 ,  B81C1/00 ,  G01B21/30 ,  G01N37/00 ,  G01Q60/38 ,  G01Q70/16 ,  H01L21/28 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  B44C1/22

CPC classification number: B81C1/00087 ,  B41J2/1603 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1631 ,  B41J2/1639 ,  B41J2/1642 ,  B41J2/1646 ,  B41J2202/13 ,  B81B2201/052

Abstract: The invention provides a method of producing a through-hole, a substrate used to produce a through-hole, a substrate having a through-hole, and a device using such a through-hole or a substrate having such a through-hole, which are characterized in that: a through-hole can be produced only by etching a silicon substrate from its back side; the opening length d can be precisely controlled to a desired value regardless of the variations in the silicon wafer thickness, and the orientation flat angle, and also regardless of the type of a silicon crystal orientation-dependent anisotropic etchant employed; high productivity, high production reproducibility, and ease of production can be achieved; a high-liberality can be achieved in the shape of the opening end even if temperature treatment is performed at a high temperature for a long time; and a high-precision through-hole can be produced regardless of the shape of a device formed on the surface of a substrate.

Abstract translation: 本发明提供一种制造通孔的方法，用于制造通孔的基板，具有通孔的基板以及使用这种通孔的装置或具有这种通孔的基板，其中 其特征在于：只能通过从其背面蚀刻硅衬底来制造通孔; 无论硅晶片厚度和取向平面角度的变化如何，也可以将开口长度d精确地控制到期望值，并且不管所采用的取决于硅晶体取向的各向异性蚀刻剂的类型如何; 可以实现高生产率，高生产重现性和易生产性; 即使长时间在高温下进行温度处理，也可以在开口形状中实现高自由度; 并且可以产生高精度通孔，而不管形成在基板表面上的器件的形状如何。

公开(公告)号：US5270125A

公开(公告)日：1993-12-14

申请号：US782705

申请日：1991-10-25

Applicant: William G. America ,  Richard R. Poole

Inventor： William G. America ,  Richard R. Poole

IPC: C23C16/34 ,  G01N25/18 ,  G03F1/22 ,  B32B9/00 ,  G03F9/00

CPC classification number: B81B3/0021 ,  C23C16/342 ,  G01N25/18 ,  G03F1/22 ,  B81B2201/0214 ,  B81B2201/0278 ,  B81B2201/052 ,  B81B2201/054 ,  B81B2203/0127 ,  B81B2203/0315 ,  Y10T428/24612 ,  Y10T428/24777

Abstract: A laminated structure includes a wafer member with a membrane attached thereto, the membrane being formed of substantially hydrogen-free boron nitride having a nominal composition B.sub.3 N. The structure may be a component in a mechanical device for effecting a mechanical function, or the membrane may form a masking layer on the wafer. The structure includes a body formed of at least two wafer members laminated together with a cavity formed therebetween, with the boron nitride membrane extending into the cavity so as to provide the structural component such as a support for a heating element or a membrane in a gas valve. In another aspect borom is selectively diffused from the boron nitride into a surface of a silicon wafer. The surface is then exposed to EDP etchant to which the diffusion layer is resistant, thereby forming a channel the wafer member with smooth walls for fluid flow.

Abstract translation: 叠层结构包括具有膜的膜片构件，膜由具有标称组成B3N的基本上无氢的氮化硼形成。 该结构可以是用于实现机械功能的机械装置中的部件，或者膜可以在晶片上形成掩模层。 该结构包括由至少两个晶片构件形成的主体，所述至少两个晶片构件在其间形成有腔，其中氮化硼膜延伸到空腔中，以便提供结构部件，例如气体中的加热元件或膜的支撑体 阀。 在另一方面，硼化物选择性地从氮化硼扩散到硅晶片的<100>表面。 然后将表面暴露于扩散层所抵抗的EDP蚀刻剂，从而形成具有平滑壁用于流体流动的晶片构件的通道。

公开(公告)号：US11787180B2

公开(公告)日：2023-10-17

申请号：US17414140

申请日：2019-04-29

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Stanley J. Wang ,  Anthony M. Fuller

IPC: B41J2/14 ,  B01L3/00 ,  B81B7/00

CPC classification number: B41J2/1433 ,  B01L3/502715 ,  B81B7/0025 ,  B01L2200/12 ,  B81B2201/052

Abstract: A microfluidic device including a fluid ejection channel defined by a fluid barrier and an orifice, or nozzle, for containing and/or passing fluids, and further including micro-electromechanical systems (MEMS) and/or electronic circuitry may be fabricated on a silicon substrate and included in a fluid ejection system. Various microfabrication techniques used for fabricating semiconductor devices may be used to manufacture such microfluidic devices.

公开(公告)号：US11746005B2

公开(公告)日：2023-09-05

申请号：US17192294

申请日：2021-03-04

Applicant: FUNAI ELECTRIC CO., LTD.

Inventor： David L. Bernard

IPC: B81C1/00 ,  B41J2/14 ,  B41J2/16 ,  B81B1/00

CPC classification number: B81C1/00087 ,  B41J2/14 ,  B41J2/162 ,  B41J2/1629 ,  B81B1/002 ,  B81B2201/052 ,  B81B2203/0353 ,  B81C2201/0132

Abstract: An ejection head chip and method for a fluid ejection device and a method for reducing a silicon shelf width between a fluid supply via and a fluid ejector stack. The ejection head chip includes a silicon substrate and a fluid ejector stack deposited on the silicon substrate, wherein at least one metal layer of the fluid ejector stack is isolated from a fluid supply via etched in the ejection head chip by an encapsulating material.

公开(公告)号：US20230241889A1

公开(公告)日：2023-08-03

申请号：US18008961

申请日：2020-06-12

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Juan Carlos Ramos ,  Stefan Enrique Lucchini

IPC: B41J2/14 ,  B81B7/00 ,  B41J2/16

CPC classification number: B41J2/14129 ,  B81B7/0025 ,  B41J2/164 ,  B41J2/1601 ,  B81B2201/052 ,  B81B2203/0338

Abstract: A microfluidic die may include a microfluidic passage and a protective layer provided adjacent to internal surfaces of the microfluidic passage. The protective layer may include a protective nano-crystalline material and a protective amorphous matrix encapsulating the protective nano-crystalline material.

公开(公告)号：US20180281414A1

公开(公告)日：2018-10-04

申请号：US15937580

申请日：2018-03-27

Applicant: CANON KABUSHIKI KAISHA

Inventor： Yoshiyuki Fukumoto ,  Atsunori Terasaki ,  Ryoji Kanri ,  Atsushi Hiramoto

IPC: B41J2/16 ,  B81C3/00 ,  B81C1/00 ,  B81B1/00 ,  B81B3/00 ,  B41J2/045

CPC classification number: B41J2/1623 ,  B41J2/045 ,  B41J2/1603 ,  B41J2/1606 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1631 ,  B41J2/1632 ,  B41J2/1634 ,  B41J2/1642 ,  B41J2/1645 ,  B41J2/1646 ,  B41J2202/22 ,  B81B1/004 ,  B81B3/0072 ,  B81B2201/052 ,  B81C1/00666 ,  B81C1/00809 ,  B81C3/001 ,  B81C2201/016 ,  B81C2203/032 ,  C23C16/405 ,  C23C16/45525

Abstract: A method for manufacturing a bonded substrate body in which an end portion of an adhesive is located at a position retreated in a direction to the inside of the bonded substrate body from an end surface of a bonding region of a first substrate and a second substrate includes forming a film on the end portion of the adhesive.

公开(公告)号：US20180230003A1

公开(公告)日：2018-08-16

申请号：US15952700

申请日：2018-04-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Ming Chen ,  Ping-Yin Liu ,  Chung-Yi Yu ,  Yeur-Luen Tu

IPC: B81B7/00 ,  B81C1/00 ,  H01L23/00

CPC classification number: B81B7/007 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2201/052 ,  B81C1/00269 ,  B81C1/00357 ,  B81C2201/013 ,  B81C2203/0109 ,  B81C2203/019 ,  B81C2203/036 ,  H01L24/03 ,  H01L24/09 ,  H01L2224/02163 ,  H01L2224/05082 ,  H01L2224/05109 ,  H01L2224/05117 ,  H01L2224/05124 ,  H01L2224/05138 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2924/01014 ,  H01L2924/01032 ,  H01L2924/1461

Abstract: An embodiment method includes forming a first plurality of bond pads on a device substrate, depositing a spacer layer over and extending along sidewalls of the first plurality of bond pads, and etching the spacer layer to remove lateral portions of the spacer layer and form spacers on sidewalls of the first plurality of bond pads. The method further includes bonding a cap substrate including a second plurality of bond pads to the device substrate by bonding the first plurality of bond pads to the second plurality of bond pads.