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公开(公告)号：US11787688B2
公开(公告)日：2023-10-17
申请号：US17099442
申请日：2020-11-16
Applicant: KNOWLES ELECTRONICS, LLC
Inventor： Sung Bok Lee , Vahid Naderyan , Bing Yu , Michael Kuntzman , Yunfei Ma , Michael Pedersen
CPC classification number: B81C1/00158 , B81B3/0021 , G01L9/0042 , H04R31/003 , B81B2201/0257 , B81B2201/0264 , B81B2203/0127 , B81C2201/0132 , B81C2201/0133
Abstract: A method of forming an acoustic transducer comprises providing a substrate and depositing a first structural layer on the substrate. The first structural layer is selectively etched to form at least one of an enclosed trench or an enclosed pillar thereon. A second structural layer is deposited on the first structural layer and includes a depression or a bump corresponding to the enclosed trench or pillar, respectively. At least the second structural layer is heated to a temperature above a glass transition temperature of the second structural layer causing the second structural layer to reflow. A diaphragm layer is deposited on the second structural layer such that the diaphragm layer includes at least one of a downward facing corrugation corresponding to the depression or an upward facing corrugation corresponding to the bump. The diaphragm layer is released, thereby forming a diaphragm suspended over the substrate.
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公开(公告)号：US11731125B2
公开(公告)日：2023-08-22
申请号：US16639867
申请日：2019-01-03
Inventor： Yue Geng , Yuelei Xiao , Hui Liao , Peizhi Cai , Jian Li , Shenkang Wu
CPC classification number: B01L3/502707 , B81C1/00071 , B01L2200/12 , B01L2300/12 , B01L2400/086 , B81C2201/0133
Abstract: A patterning method of a film is disclosed. The method including: providing a film including a first surface; forming n etching barrier layers on the first surface of the film, and n is an integer larger than or equal to 2; and performing n etching processes on the film to form a recessed structure on the first surface using the n etching barrier layers as masks, the recessed structure includes n bottom surfaces respectively having different depths. Two adjacent etching processes of the n etching processes include a previous etching process and a subsequent etching process, and after the previous etching process is completed, a part of the n etching barrier layers is removed to form a mask for the subsequent etching process; a material of the part of the n etching barrier layers which is removed is different from a material of the mask of the subsequent etching process.
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223.发明申请公开(公告)号：US20180170748A1
公开(公告)日：2018-06-21
申请号：US15899785
申请日：2018-02-20
Applicant: Globalfoundries Singapore Pte. Ltd.
Inventor： Siddharth Chakravarty , Rakesh Kumar , Pradeep Yelehanka
CPC classification number: B81C1/00293 , B81B7/0074 , B81B2203/0315 , B81C2201/0105 , B81C2201/0132 , B81C2201/0133 , B81C2203/0136
Abstract: Semiconductor devices with enclosed cavities and methods for fabricating semiconductor devices with enclosed cavities are provided. In an embodiment, a method for fabricating a semiconductor device with a cavity includes providing a substrate terminating at an uppermost surface and forming a sacrificial structure over the uppermost substrate of the substrate. The method includes forming a device structure overlying a lower portion of the sacrificial structure, overlying the uppermost surface of the substrate, and underlying an upper portion of the sacrificial structure. The method also includes depositing a permeable layer over the sacrificial structure, the device structure and the substrate. Further, the method includes etching the sacrificial structure through the permeable layer to form the cavity, wherein the cavity has an outer surface completely bounded by the substrate, the device structure, and the permeable layer.
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224.发明申请公开(公告)号：US20180148325A1
公开(公告)日：2018-05-31
申请号：US15591652
申请日：2017-05-10
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Enri Duqi , Lorenzo Baldo , Domenico Giusti
CPC classification number: B81C1/00238 , B81B7/0051 , B81B7/007 , B81B2201/0235 , B81B2201/0242 , B81B2201/0264 , B81B2203/0118 , B81B2203/0127 , B81B2203/0315 , B81B2207/012 , B81B2207/07 , B81C2201/0133 , B81C2203/032 , B81C2203/035 , B81C2203/0792
Abstract: An integrated device includes: a first die; a second die coupled in a stacked way on the first die along a vertical axis; a coupling region arranged between facing surfaces of the first die and of the second die, which face one another along the vertical axis and lie in a horizontal plane orthogonal to the vertical axis, for mechanical coupling of the first and second dies; electrical-contact elements carried by the facing surfaces of the first and second dies, aligned in pairs along the vertical axis; and conductive regions arranged between the pairs of electrical-contact elements carried by the facing surfaces of the first and second dies, for their electrical coupling. Supporting elements are arranged at the facing surface of at least one of the first and second dies and elastically support respective electrical-contact elements.
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公开(公告)号：US09919916B2
公开(公告)日：2018-03-20
申请号：US15031957
申请日：2014-10-15
Applicant: Semitechnologies Limited
CPC classification number: B81C1/00111 , A61M37/0015 , A61M2037/003 , A61M2037/0053 , B81B2201/055 , B81C2201/0132 , B81C2201/0133 , B81C2201/0159 , B81C2201/0176 , B81C2201/0181 , C23C16/402
Abstract: A method of forming microneedles where through a series of coating and etching processes microneedles are formed from a surface as an array. The microneedles have a bevelled end and bore which are formed as part of the process with no need to use a post manufacturing process to finish the microneedle.
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Patent Agency Ranking
公开(公告)号：US09917148B2
公开(公告)日：2018-03-13
申请号：US14933958
申请日：2015-11-05
Applicant: International Business Machines Corporation
Inventor： Emmanuel Delamarche , Bilge Eker , Yuksel Temiz
IPC: H01L21/4763 , H01L29/04 , H01L29/16 , F16K99/00 , B01L3/00
CPC classification number: H01L29/045 , B01L3/502707 , B01L2300/0816 , B01L2300/0874 , B01L2300/0887 , B81B2201/051 , B81B2203/0338 , B81B2203/0353 , B81C1/00087 , B81C2201/0133 , F16K99/0001 , F16K2099/0074 , H01L29/04 , H01L29/16
Abstract: The present invention is notably directed to a method of fabrication of a microfluidic chip (1), comprising: providing (S10-S20) a wafer (10, 12) of semiconductor material having a diamond cubic crystal structure, exhibiting two opposite main surfaces (S1, S2), one on each side of the wafer, and having, each, a normal in the or direction; and performing (S30) self-limited, anisotropic wet etching steps on each of the two main surfaces on each side of the wafer, to create a via (20, 20a) extending transversely through the thickness of the wafer, at a location such that the resulting via connects an in-plane microchannel (31) on a first one (S1) of the two main surfaces to a second one (S2) of the two main surfaces, the via exhibiting slanted sidewalls (20s) as a result of the self-limited wet etching. The invention further concerns microfluidic chips accordingly obtained.
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公开(公告)号：US09868628B2
公开(公告)日：2018-01-16
申请号：US15066799
申请日：2016-03-10
Inventor： Yu-Chia Liu , Chia-Hua Chu , Chun-Wen Cheng
CPC classification number: B81B7/0006 , B81B7/0051 , B81B2201/0257 , B81B2201/0264 , B81B2201/0271 , B81C1/00246 , B81C2201/0132 , B81C2201/0133 , B81C2201/0176 , B81C2201/0181 , B81C2201/112 , B81C2203/0714 , B81C2203/0735
Abstract: Representative methods for sealing MEMS devices include depositing insulating material over a substrate, forming conductive vias in a first set of layers of the insulating material, and forming metal structures in a second set of layers of the insulating material. The first and second sets of layers are interleaved in alternation. A dummy insulating layer is provided as an upper-most layer of the first set of layers. Portions of the first and second set of layers are etched to form void regions in the insulating material. A conductive pad is formed on and in a top surface of the insulating material. The void regions are sealed with an encapsulating structure. At least a portion of the encapsulating structure is laterally adjacent the dummy insulating layer, and above a top surface of the conductive pad. An etch is performed to remove at least a portion of the dummy insulating layer.
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228.发明授权公开(公告)号：US09842749B2
公开(公告)日：2017-12-12
申请号：US15324670
申请日：2015-11-17
Applicant: Beijing University of Technology
Inventor： Guangsheng Guo , Siyu Wang , Qiaosheng Pu , Xiayan Wang
CPC classification number: H01L21/67028 , B81C1/00928 , B81C3/001 , B81C3/002 , B81C2201/0102 , B81C2201/0128 , B81C2201/0133 , B81C2201/019 , B81C2203/051 , H01L21/68
Abstract: The plasma-assisted method of precise alignment and pre-bonding for microstructure of glass and quartz microchip belongs to micromachining and bonding technologies of the microchip. The steps of which are as follows: photoresist and chromium layers on glass or quartz microchip are completely removed followed by sufficient cleaning of the surface with nonionic surfactant and quantities of ultra-pure water. Then the surface treatment is proceeded for an equipping surface with high hydrophily with the usage of plasma cleaning device. Under the drying condition, the precise alignment is accomplished through moving substrate and cover plate after being washed with the help of microscope observation. Further on, to achieve precise alignment and pre-bonding of the microstructure of glass and quartz microchip, a minute quantity of ultrapure water is instilled into a limbic crevice for adhesion, and entire water is completely wiped out by vacuum drying following sufficient squeezing. Based on the steps above, it is available to achieve permanent bonding by further adopting thermal bonding method. In summary, it takes within 30 min to finish the whole operation of precise alignment and pre-bonding by this method. Besides, this method is of great promise because of its speediness, efficiency, easy maneuverability, operational safety and wide applications.
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公开(公告)号：US09824834B2
公开(公告)日：2017-11-21
申请号：US14883836
申请日：2015-10-15
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Stephen E. Luce , Anthony K. Stamper
CPC classification number: B81C1/00698 , B81C1/0015 , B81C1/00166 , B81C1/00523 , B81C2201/0132 , B81C2201/0133 , B81C2201/0145 , B81C2201/0154 , B81C2203/0145 , H01H1/0036 , H01H1/58 , H01H11/00 , H01H49/00 , H01H59/00 , H01H59/0009 , H01H2059/0018 , Y10T29/49105
Abstract: An approach includes a method of fabricating a switch. The approach includes forming a first fixed electrode and a second fixed electrode, forming a first cantilevered electrode aligned vertically over the first fixed electrode and the second fixed electrode, and operable to directly contact the second fixed electrode upon an application of a voltage to the first fixed electrode, forming a second cantilevered electrode aligned vertically over the second fixed electrode, and which has an end that overlaps the first cantilevered electrode, and forming a hermetically sealed volume encapsulating the first fixed electrode, the second fixed electrode, the first cantilevered electrode, and the second cantilevered electrode.
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公开(公告)号：US20170260042A1
公开(公告)日：2017-09-14
申请号：US15066799
申请日：2016-03-10
Inventor： Yu-Chia Liu , Chia-Hua Chu , Chun-Wen Cheng
CPC classification number: B81B7/0006 , B81B7/0051 , B81B2201/0257 , B81B2201/0264 , B81B2201/0271 , B81C1/00246 , B81C2201/0132 , B81C2201/0133 , B81C2201/0176 , B81C2201/0181 , B81C2201/112 , B81C2203/0714 , B81C2203/0735
Abstract: Representative methods for sealing MEMS devices include depositing insulating material over a substrate, forming conductive vias in a first set of layers of the insulating material, and forming metal structures in a second set of layers of the insulating material. The first and second sets of layers are interleaved in alternation. A dummy insulating layer is provided as an upper-most layer of the first set of layers. Portions of the first and second set of layers are etched to form void regions in the insulating material. A conductive pad is formed on and in a top surface of the insulating material. The void regions are sealed with an encapsulating structure. At least a portion of the encapsulating structure is laterally adjacent the dummy insulating layer, and above a top surface of the conductive pad. An etch is performed to remove at least a portion of the dummy insulating layer.
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