公开(公告)号：EP0335565B1

公开(公告)日：1994-06-15

申请号：EP89302794.6

申请日：1989-03-21

Applicant: Hitachi Chemical Co., Ltd.

Inventor： Takahashi, Hiroshi ,  Takanezawa, Shin ,  Kanno, Masao ,  Iwasaki, Yorio ,  Okamura, Toshirou ,  Nakaso, Akishi ,  Hasegawa, Kiyoshi

IPC: H05K3/18 ,  H05K3/42

CPC classification number: H05K3/426 ,  H05K1/0373 ,  H05K3/181 ,  H05K3/184 ,  H05K3/387 ,  H05K2201/0236 ,  H05K2201/0344 ,  H05K2203/0709 ,  H05K2203/1407 ,  H05K2203/1415

公开(公告)号：EP0559384A2

公开(公告)日：1993-09-08

申请号：EP93301437.5

申请日：1993-02-25

Applicant: AT&T Corp.

Inventor： Fuchs, Harold E.

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L23/4985 ,  H01L2224/16 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15173 ,  H05K1/0393 ,  H05K1/112 ,  H05K3/0032 ,  H05K3/243 ,  H05K3/426 ,  H05K2201/0154 ,  H05K2201/0344 ,  H05K2201/10674 ,  H05K2203/0455

Abstract: Disclosed is a method for fabricating devices, and the resulting products, using Tape Automated Bonding (TAB) technology. Via holes (30) are formed through a flexible insulating layer (11), such as polyimide, and are plated through when conductive fingers (12) are formed on one surface of the layer. The resulting structure is then bonded to a semiconductor chip (41) by means of the conductive pads (20) formed on the surface of the insulating layer opposite to the conductive fingers.

Abstract translation: 公开了一种用于制造器件的方法，以及使用带式自动接合（TAB）技术的所得产品。 通孔（30）通过诸如聚酰亚胺的柔性绝缘层（11）形成，并且当在该层的一个表面上形成导电指状物（12）时，通孔（30）被电镀。 然后通过形成在与导电指状物相对的绝缘层的表面上的导电焊盘（20）将所得到的结构结合到半导体芯片（41）。

公开(公告)号：US20240292533A1

公开(公告)日：2024-08-29

申请号：US18572428

申请日：2022-06-13

Applicant: KYOCERA Corporation

Inventor： Hidetoshi YUGAWA

IPC: H05K1/09 ,  H05K1/02 ,  H05K3/42

CPC classification number: H05K1/09 ,  H05K1/0271 ,  H05K3/427 ,  H05K2201/0344 ,  H05K2201/0352 ,  H05K2203/072 ,  H05K2203/0726

Abstract: A wiring board according to the present disclosure includes an insulation layer, and a wiring conductor positioned on the insulation layer. The wiring conductor includes a phosphorus-containing electroless copper-plating layer positioned on the insulation layer, a nickel-containing electroless copper-plating layer positioned on the phosphorus-containing electroless copper-plating layer, and an electrolytic copper-plating layer positioned on the nickel-containing electroless copper-plating layer.

公开(公告)号：US09591753B2

公开(公告)日：2017-03-07

申请号：US14849614

申请日：2015-09-10

Applicant: Subtron Technology Co., Ltd.

Inventor： Chin-Sheng Wang ,  Ching-Sheng Chen ,  Mei-Chin Chang ,  Ching-Ta Chen

IPC: H05K1/09 ,  H05K1/11 ,  H05K3/18

CPC classification number: H05K1/09 ,  H05K1/111 ,  H05K3/181 ,  H05K3/188 ,  H05K3/244 ,  H05K2201/0338 ,  H05K2201/0344 ,  H05K2201/09472 ,  H05K2201/099 ,  H05K2203/072

Abstract: A circuit board includes a substrate, a patterned copper layer, a phosphorous-containing electroless plating palladium layer, an electroless plating palladium layer and an immersion plating gold layer. The patterned copper layer is disposed on the substrate. The phosphorous-containing electroless plating palladium layer is disposed on the patterned copper layer, wherein in the phosphorous-containing electroless plating palladium layer, a weight percentage of phosphorous is in a range from 4% to 6%, and a weight percentage of palladium is in a range from 94% to 96%. The electroless plating palladium layer is disposed on the phosphorous-containing electroless plating palladium layer, wherein in the electroless plating palladium layer, a weight percentage of palladium is 99% or more. The immersion plating gold layer is disposed on the electroless plating palladium layer.

Abstract translation: 电路板包括基板，图案化铜层，含磷化学镀钯层，无电镀钯层和浸镀金层。 图案化铜层设置在基板上。 含磷化学镀钯层设置在图案化的铜层上，其中，在含磷化学镀钯层中，磷的重量百分比为4〜6％，钯的重量百分比为 在94％至96％的范围内。 无电镀钯层配置在含磷化学镀钯层上，其中，在化学镀钯层中，钯的重量百分比为99％以上。 浸镀金层设置在化学镀钯层上。

公开(公告)号：US09282635B2

公开(公告)日：2016-03-08

申请号：US14669329

申请日：2015-03-26

Applicant: IBIDEN CO., LTD.

Inventor： Toyotaka Shimabe ,  Shunsuke Sakai

IPC: H05K7/00 ,  H05K1/02 ,  H05K1/18 ,  H05K3/46

CPC classification number: H05K1/0284 ,  H01L21/568 ,  H01L24/19 ,  H01L24/25 ,  H01L2224/04105 ,  H01L2224/16227 ,  H01L2224/2518 ,  H01L2224/82039 ,  H01L2924/15313 ,  H05K1/185 ,  H05K3/4602 ,  H05K3/4697 ,  H05K2201/0344 ,  H05K2201/09036 ,  H05K2201/09145 ,  H05K2201/09154 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/10522 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/4913

Abstract: A multilayer wiring board with a built-in electronic component includes a substrate, a conductor layer formed on surface of the substrate, one or more electronic components positioned in a cavity formed through the substrate, an insulating layer formed on the substrate such that the insulating layer is formed on the component in the cavity, and a wiring layer formed on the insulating layer. The conductor layer has an opening formed such that the cavity is formed in the opening of the conductor layer and that the conductor layer has a first side in the opening and a second side in the opening on the opposite side across the cavity, and the cavity is formed in the opening of the conductor layer such that width between the cavity and the first side of the conductor layer is greater than width between the cavity and the second side of the conductor layer.

Abstract translation: 具有内置电子部件的多层布线基板包括基板，形成在基板的表面上的导体层，位于通过基板形成的空腔中的一个或多个电子部件，形成在基板上的绝缘层， 在空腔中的部件上形成层，以及形成在绝缘层上的布线层。 导体层具有形成为使得空腔形成在导体层的开口中并且导体层在开口中具有第一侧的开口，并且在开口中的相对于空腔的开口中的第二侧，并且空腔 形成在导体层的开口中，使得空腔和导体层的第一侧之间的宽度大于导体层的空腔和第二侧之间的宽度。

公开(公告)号：US20150296616A1

公开(公告)日：2015-10-15

申请号：US14251486

申请日：2014-04-11

Applicant: QUALCOMM Incorporated

Inventor： Houssam Wafic Jomaa ,  Omar James Bchir ,  Chin-Kwan Kim

IPC: H05K1/11 ,  H05K3/42 ,  H05K1/02

CPC classification number: H05K1/112 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0298 ,  H05K3/422 ,  H05K3/425 ,  H05K3/429 ,  H05K2201/0344 ,  H05K2201/09036 ,  H05K2201/10378

Abstract: Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect, a first cavity, and a first electroless metal layer. The first dielectric layer includes a first surface and a second surface. The first interconnect is on the first surface of the substrate layer. The first cavity traverses the first surface of the first dielectric layer. The first electroless metal layer is formed at least partially in the first cavity. The first electroless metal layer defines a second interconnect embedded in the first dielectric layer. In some implementations, the substrate further includes a core layer. The core layer includes a first surface and a second surface. The first surface of the core layer is coupled to the second surface of the first dielectric layer. In some implementations, the substrate further includes a second dielectric layer.

Abstract translation: 一些新颖特征涉及包括第一介电层，第一互连，第一空腔和第一无电金属层的基板。 第一电介质层包括第一表面和第二表面。 第一互连在衬底层的第一表面上。 第一空腔穿过第一介电层的第一表面。 第一无电金属层至少部分地形成在第一腔中。 第一无电金属层限定嵌入在第一介电层中的第二互连。 在一些实施方案中，衬底还包括芯层。 芯层包括第一表面和第二表面。 芯层的第一表面耦合到第一介电层的第二表面。 在一些实施方案中，衬底还包括第二介电层。

公开(公告)号：US20150282305A1

公开(公告)日：2015-10-01

申请号：US14669329

申请日：2015-03-26

Applicant: IBIDEN CO., LTD.

Inventor： Toyotaka SHIMABE ,  Shunsuke SAKAI

IPC: H05K1/02 ,  H05K3/46 ,  H05K1/18

CPC classification number: H05K1/0284 ,  H01L21/568 ,  H01L24/19 ,  H01L24/25 ,  H01L2224/04105 ,  H01L2224/16227 ,  H01L2224/2518 ,  H01L2224/82039 ,  H01L2924/15313 ,  H05K1/185 ,  H05K3/4602 ,  H05K3/4697 ,  H05K2201/0344 ,  H05K2201/09036 ,  H05K2201/09145 ,  H05K2201/09154 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/10522 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/4913

Abstract: A multilayer wiring board with a built-in electronic component includes a substrate, a conductor layer formed on surface of the substrate, one or more electronic components positioned in a cavity formed through the substrate, an insulating layer formed on the substrate such that the insulating layer is formed on the component in the cavity, and a wiring layer formed on the insulating layer. The conductor layer has an opening formed such that the cavity is formed in the opening of the conductor layer and that the conductor layer has a first side in the opening and a second side in the opening on the opposite side across the cavity, and the cavity is formed in the opening of the conductor layer such that width between the cavity and the first side of the conductor layer is greater than width between the cavity and the second side of the conductor layer.

Abstract translation: 具有内置电子部件的多层布线基板包括基板，形成在基板的表面上的导体层，位于通过基板形成的空腔中的一个或多个电子部件，形成在基板上的绝缘层， 在空腔中的部件上形成层，以及形成在绝缘层上的布线层。 导体层具有形成为使得空腔形成在导体层的开口中并且导体层在开口中具有第一侧的开口，并且在开口中的相对于空腔的开口中的第二侧，并且空腔 形成在导体层的开口中，使得空腔和导体层的第一侧之间的宽度大于导体层的空腔和第二侧之间的宽度。

公开(公告)号：US20150181710A1

公开(公告)日：2015-06-25

申请号：US14408205

申请日：2013-03-13

Applicant: HSIO TECHNOLOGIES, LLC

Inventor： James Rathburn

IPC: H05K1/18 ,  H05K3/10 ,  H05K1/02

CPC classification number: H05K1/181 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H05K1/0216 ,  H05K1/0256 ,  H05K1/0284 ,  H05K1/16 ,  H05K3/107 ,  H05K3/4664 ,  H05K3/4694 ,  H05K2201/0344 ,  H05K2201/10674 ,  H05K2201/10734 ,  Y10T29/49155 ,  H01L2924/00014

Abstract: A high density region for a low density circuit. At least a first liquid dielectric layer is deposited on the first surface of a first circuitry layer. The dielectric layer is imaged to create plurality of first recesses. Surfaces of the first recesses are plated electro-lessly with a conductive material to form first conductive structures electrically coupled to, and extending generally perpendicular to, the first circuitry layer. A plating resist is applied. A conductive material is electro-plated to the first conductive structure to substantially fill the first recesses, and the plating resist is removed.

Abstract translation: 低密度电路的高密度区域。 至少第一液体介电层沉积在第一电路层的第一表面上。 对电介质层进行成像以产生多个第一凹槽。 第一凹槽的表面电镀不良地与导电材料电镀以形成电耦合到第一电路层并且大致垂直于第一电路层延伸的第一导电结构。 应用电镀抗蚀剂。 将导电材料电镀到第一导电结构以基本上填充第一凹部，并且去除电镀抗蚀剂。

公开(公告)号：US08935850B2

公开(公告)日：2015-01-20

申请号：US13776024

申请日：2013-02-25

Applicant: Ibiden Co., Ltd.

Inventor： Masahiro Kaneko ,  Satoru Kose ,  Hirokazu Higashi

IPC: H05K3/02 ,  H05K3/10 ,  H05K1/11 ,  H01L21/683 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H05K3/38 ,  H05K3/00

CPC classification number: H05K3/42 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49866 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/32057 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48644 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/85001 ,  H01L2224/85385 ,  H01L2224/85444 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K1/0313 ,  H05K1/113 ,  H05K1/115 ,  H05K3/007 ,  H05K3/108 ,  H05K3/22 ,  H05K3/388 ,  H05K2201/0344 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2203/072 ,  H05K2203/1377 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A method for manufacturing a printed wiring board includes forming a removable layer on a support substrate, forming an interlayer resin insulation layer on the removable layer, forming a penetrating hole in the interlayer resin insulation layer, forming a first conductive layer on the interlayer resin insulation layer and on a side wall of the penetrating hole, forming a conductive circuit on the interlayer resin insulation layer, forming a via conductor in the penetrating hole, removing the support substrate from the interlayer resin insulation layer by using the removable layer, forming a protruding portion of the via conductor protruding from a surface of the interlayer resin insulation layer, and forming a surface-treatment coating on a surface of the protruding portion of the via conductor.

Abstract translation: 一种制造印刷电路板的方法，包括在支撑基板上形成可移除层，在可移除层上形成层间树脂绝缘层，在层间树脂绝缘层中形成贯通孔，在层间树脂绝缘层上形成第一导电层 在所述贯通孔的侧壁上形成导电电路，在所述层间树脂绝缘层上形成导通电路，在所述贯通孔中形成通路导体，使用所述可移除层从所述层间树脂绝缘层除去所述支撑基板， 所述通孔导体的一部分从所述层间树脂绝缘层的表面突出，并且在所述通孔导体的所述突出部分的表面上形成表面处理涂层。

公开(公告)号：US20140014521A1

公开(公告)日：2014-01-16

申请号：US14029637

申请日：2013-09-17

Applicant: ARAKAWA CHEMICAL INDUSTRIES, LTD.

Inventor： Akihisa HAMAZAWA ,  Koji Nishimura ,  Hideki Goda

IPC: H05K1/02

CPC classification number: H05K1/0277 ,  H05K1/0346 ,  H05K1/0373 ,  H05K1/0393 ,  H05K3/108 ,  H05K2201/0154 ,  H05K2201/0209 ,  H05K2201/0344 ,  H05K2201/068 ,  Y10T29/49124

Abstract: An object of the present invention is to provide a flexible circuit board that maintains high insulation reliability, exhibits high wiring adhesion, has low thermal expansion, and allows the formation of a fine circuit thereon. Specifically, the present invention provides a flexible circuit board, wherein at least a nickel plating layer is laminated on a polyimide film to form a polyimide film provided with a nickel plating layer and a wiring pattern is applied to the nickel plating layer thereof. The polyimide film has a thermal expansion coefficient of 0 to 8 ppm/° C. in the temperature range from 100 to 200° C., and the nickel plating layer has a thickness of 0.03 to 0.3 μm.

Abstract translation: 本发明的目的是提供一种保持高绝缘可靠性，显示出高布线附着力，低热膨胀性并且允许在其上形成微细电路的柔性电路板。 具体地说，本发明提供一种挠性电路基板，其中，在聚酰亚胺膜上层叠有至少一层镍镀层，形成具有镀镍层的聚酰亚胺膜，并且对其镀镍层施加布线图案。 聚酰亚胺膜在100〜200℃的温度范围内的热膨胀系数为0〜8ppm /℃，镍镀层的厚度为0.03〜0.3μm。