Abstract:
A high-speed, high-power modular router is disclosed. As opposed to conventional designs using optical backplane signaling and/or bus bars for power distribution, the disclosed embodiments combine high-power, low-noise power distribution with high-speed signal routing in a common backplane. Disclosed backplane features allow backplane signaling at 2.5 Gbps or greater on electrical differential pairs distributed on multiple high-speed signaling layers. Relatively thick power distribution layers are embedded within the backplane, shielded from the high-speed signaling layers by digital ground layers and other shielding features. A router using such a backplane provides a level of performance and economy that is believed to be unattainable by the prior art.
Abstract:
A semiconductor device comprising a substrate including a metal portion and a resin portion and having a plurality of through holes formed in the resin portion, conductive members formed within the through holes, a semiconductor chip attached to one surface of the substrate, and a plurality of solder balls attached to the other surface of the substrate. The semiconductor chip and solder balls are electrically connected through the conductive members.
Abstract:
In accordance with this invention a procelain coated metal board is provided which has flat surfaces and further has electrical connections between the face and reverse surfaces of the board. In accordance with a further aspect of this invention the boards of this invention are obtained by a method in which the connecting pins are sealed in a spaced relationship in apertures in the metal core of the board and insulated from the core prior to the application of the procelain to the surfaces of the core.
Abstract:
PURPOSE: An electromagnetic wave shielding substrate is provided to efficiently shield the emission of an electromagnetic wave by forming an electromagnetic band gap structure along the edge of a substrate. CONSTITUTION: A conductive layer(110) is comprised of a plurality of conductive plates. A metal layer(300) is arranged on the upper or lower side of the conductive layer and includes a stitching pattern(310) which electrically connects a first conductive plate(110a) and a second conductive plate(110b). The first conductive plate is electrically connected to the second conductive plate through a first via(510) and a second via(530). All conductive plates formed on the conductive layer are electrically connected to each other through the stitching pattern.
Abstract:
PURPOSE: A semiconductor chip package having a through electrode and a printed circuit board are provided to change characteristic impedance of a through electrode by controlling arrangement of the through electrode. CONSTITUTION: A semiconductor chip package(100) having a through electrode includes a signal electrode, a power electrode, and a ground electrode. The signal electrode(132) penetrates a semiconductor chip, and delivers a signal to the semiconductor chip(110). The power electrode(134) and the ground electrode(136) penetrate the semiconductor chip, and deliver a power and a ground to the semiconductor chip. The power electrode and the ground electrode are positioned in an adjacent distance from each signal electrode.
Abstract:
A wiring structure of laminated capacitors is provided to enhance efficiency in radio frequency applications by reducing a surface area of a capacitor and reducing parasitic capacitance. A plurality of conductive layers includes a top conductive layer and a bottom conductive layer. The conductive layers include a set of first conductive layers and a set of second conductive layers. A power via(440) is extended along a thickness direction of the laminated capacitor and is arranged from the top conductive layer to the bottom conductive layer. The power via is electrically coupled to the first conductive layers. A ground via(450) is extended along the thickness direction of the laminated capacitor and is arranged from the top conductive layer to the bottom conductive layer. The ground via is electrically coupled to the second conductive layers. A supplemental via(460) is positioned between the power via and the ground via. The supplemental via is shorter in length than the power via and the ground via. The supplemental via is electrically coupled to one of the first conductive layers and the second conductive layers.
Abstract:
고속 차동 신호 응용에서 유용하고, 바이어 배열체 또는 회로 트레이스 진출 구조물을 사용하는, 회로 기판 설계가 개시된다. 바이어 배열체에서, 차동 신호 쌍 바이어 세트 및 관련된 접지는 반복 패턴으로 서로 인접하여 배열된다. 각각의 쌍의 차동 신호 바이어는, 차동 신호 바이어가 그 관련된 접지 바이어에 전기적으로 커플링하는 데 우선권을 나타내도록, 인접한 차동 신호 쌍의 관련된 접지 사이의 공간보다 그 관련된 접지 바이어에 더 인접하게 이격된다. 회로 트레이스 진출 구조물은 트레이스가 이어서 전도성 트레이스의 전송 라인 부분과 만나서 접합하는 경로를 따르도록 차동 신호 바이어의 회로 트레이스의 진출부를 포함한다. 트레이스, 회로 기판, 바이어, 패턴, 접지, 진출부