公开(公告)号：WO2003086957A1

公开(公告)日：2003-10-23

申请号：PCT/FR2003/001012

申请日：2003-04-01

Applicant: THALES ,  LEFORT, Pierre-Olivier ,  THOMAS, Isabelle

Inventor： LEFORT, Pierre-Olivier ,  THOMAS, Isabelle

IPC: B81B7/00

CPC classification number: B81B7/0038 ,  B81C2201/0115

Abstract: L'invention concerne un procédé de fabrication d'une microstructure comportant une cavité sous vide. II comporte les étapes suivantes consistant à : a) réaliser à partir d'une première plaque de silicium, une zone de silicium poreux destinée à constituer totalement ou en partie une paroi de la cavité et apte à absorber des gaz résiduels de la cavité, b) assembler la première plaque de silicium à une deuxième plaque, de manière à réaliser la cavité.

Abstract translation: 本发明涉及一种用于生产包括真空腔的微结构的方法。 本发明的方法包括以下步骤：a）从第一硅片产生多孔硅区域，以便全部或部分地形成空腔的壁并吸收所述空腔的残余气体; b）第一硅片与第二硅片组装以产生所述空腔。

公开(公告)号：WO02051742A3

公开(公告)日：2003-05-08

申请号：PCT/DE0104692

申请日：2001-12-13

Applicant: BOSCH GMBH ROBERT ,  BENZEL HUBERT ,  WEBER HERIBERT ,  ARTMANN HANS ,  SCHAEFER FRANK

Inventor： BENZEL HUBERT ,  WEBER HERIBERT ,  ARTMANN HANS ,  SCHAEFER FRANK

IPC: B81B3/00 ,  B81C1/00 ,  H01L29/84

CPC classification number: B81C1/00182 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C2201/0114 ,  B81C2201/0115 ,  B81C2201/0178

Abstract: The invention relates to a micromechanical component comprising: a substrate (1); a monocrystalline layer (10), which is provided above the substrate (1) and which has a membrane region (10a); a cavity (50) that is provided underneath the membrane region (10a), and; one or more porous regions (150; 150'), which are provided inside the monocrystalline layer (10) and which have a doping (n ; p ) that is higher than that of the surrounding layer (10).

Abstract translation: 本发明提供了一种具有衬底（1）的微机械部件; 一个所提供的单晶层（10），其具有隔膜部（10A）在所述衬底（1）的上方; 一个设置在所述空腔的膜区域（10a）的下面（50）; 和一个或多个单晶层（10）的内部设置的多孔区域（150; 150“），其具有相对于增加的掺杂的周边层（10）（N <+>; P <+>）。

公开(公告)号：WO02051741A2

公开(公告)日：2002-07-04

申请号：PCT/DE2001/004602

申请日：2001-12-06

IPC: G01P9/04 ,  B81B3/00 ,  B81C1/00 ,  C23F1/24 ,  G01C19/56 ,  G01P15/12 ,  H01L21/306 ,  H01L29/84

CPC classification number: B81C1/00492 ,  B81B2201/0235 ,  B81B2203/0315 ,  B81C2201/0115 ,  Y10S438/96

Abstract: The invention relates to a method for producing a semiconductor component (330; 400; 500; 600; 700; 800; 900; 1000; 1100) such as especially, a multiple layer semiconductor component, having a movable mass or an oscillator structure (501, 502; 701, 702), of the type described in the corresponding independent patent claim; and to a semiconductor component produced according to this method. The aim of the invention is to provide a simple and economical means of producing a micromechanical component with monocrystalline oscillator structures (501, 502; 601, 702) such as especially, an acceleration sensor or a rotation rate sensor, in the field of surface micromechanics. To this end, the inventive method provides that in a first step, a first porous layer (301; 901) is formed in the semiconductor component and in a second step, a cavity or a cavern (302; 1101) is formed in the semiconductor component, beneath or from the first porous layer (301).

Abstract translation: 本发明涉及一种制造半导体器件（330; 400; 500; 600; 700; 800; 900; 1000; 1100）的方法，特别是多层半导体组件，并且其中特别地半导体部件根据制造的半导体器件的可移动通过的方法， 有，根据独立权利要求而言，质量或换能器结构（701，702 501，502）的前同步码。 具有微机械部件单个晶体振荡器结构（501，502; 601，702）能够在表面微机械加工来生产，如在特定的加速度传感器或旋转速率传感器，容易且廉价地，在本发明的方法提供了在第一步骤（第一多孔层 301; 901）中的半导体器件，并且在第二步骤中形成，空腔或腔体（302; 1101）是由或从半导体器件中的第一多孔差（301）形成。

公开(公告)号：WO0146066A3

公开(公告)日：2002-04-04

申请号：PCT/DE0004454

申请日：2000-12-14

Applicant: BOSCH GMBH ROBERT ,  REICHENBACH FRANK ,  PINTER STEFAN ,  HENNING FRANK ,  ARTMANN HANS ,  BAUMANN HELMUT ,  LAERMER FRANZ ,  OFFENBERG MICHAEL ,  BISCHOPINK GEORG

Inventor： REICHENBACH FRANK ,  PINTER STEFAN ,  HENNING FRANK ,  ARTMANN HANS ,  BAUMANN HELMUT ,  LAERMER FRANZ ,  OFFENBERG MICHAEL ,  BISCHOPINK GEORG

IPC: B81B3/00 ,  B81B7/00 ,  B81C1/00 ,  G01P15/08

CPC classification number: B81C1/00293 ,  B81B2201/0228 ,  B81B2207/095 ,  B81C2201/0115 ,  B81C2203/0136 ,  B81C2203/0145

Abstract: According to the invention, the cover (13) of the inventive sensor is made of a first layer (32) (deposition layer) which is transparent to an etching to reaction products and has a hermetically sealed second layer (34) (sealing layer) located thereover. In the method according to the invention, at least the sensor chamber (28) is located in the base wafer (11) is filled with an oxide (30), in particular CVD oxide or porous oxide after a structure (26) has been established. The sensor chamber (28)is covered with a first layer (32) in particular a polysilicon layer which is or has been made transparent to the etching medium and the reaction products (deposition layer). The oxide (30) in the sensor chamber (28) is removed by an etching medium which etches through the deposition layer (32). A second layer (34) (sealing layer) is subsequently applied to the deposition layer (32) which hermetically seals the sensor chamber (28). Said second layer is in particular made of a metal or an insulator.

Abstract translation: 据设想，在本发明的传感器，由透明的盖（13）的蚀刻介质和反应产物中的第一层（32）（分离层）和上覆的气密地密封的第二层（34）（密封层），并且本发明的方法 至少在基底晶片（11）建立结构之后（26），现有的传感器腔室（28）填充有具有氧化物（30），特别是CVD氧化物或多孔氧化物，所述传感器室（28），一个用于蚀刻介质和反应产物 透明或随后作出透明的第一层（32）（分离层），特别是多晶硅，被覆盖，这是在所述传感器室（28）通过所述分离层（32）的氧化物（30）通过蚀刻介质和随后的第二层（去世 由金属或绝缘体（在沉积层32上）的34）（密封层），特别是施加到浅草 rraum（28）气密地密封。

公开(公告)号：WO0180286A3

公开(公告)日：2002-02-07

申请号：PCT/US0112281

申请日：2001-04-17

Applicant: PENN STATE RES FOUND

Inventor： FONASH STEPHEN J ,  KALKAN ALI KAAN ,  BAE SANGHOON ,  HAYES DAN ,  NAM WOOK JUN ,  CHANG KYUHWAN ,  LEE YOUNGCHUL

IPC: B81B3/00 ,  B81C1/00 ,  C23C16/24 ,  C23C16/511 ,  H01L21/306 ,  H01M8/02 ,  B05D5/12

CPC classification number: B81C1/0038 ,  B81C99/008 ,  B81C2201/0109 ,  B81C2201/0115 ,  B81C2203/0127 ,  C23C16/24 ,  C23C16/511

Abstract: This invention uses large surface to volume ratio materials for separation, release layer, and sacrificial material applications. The invention outlines the material concept, application designs, and fabrication methodologies. The invention is demonstrated using deposited column/void network materials as examples of large surface to volume ratio materials. In a number of the specific applications discussed, it is shown that it is advantageous to create structures on a laminate on a mother substrate and then, using the separation layer material approach, to separate this laminate from the mother substrate using the present separation scheme. It is also shown that the present materials have excellent release layer utility. In a number of applications it is also shown how the approach can be used to uniquely form cavities, channels, air-gaps, and related structures in or on various substrates. Further, it is demonstrated that it also can be possible and advantageous to combine the schemes for cavity formation with the scheme for laminate separation.

Abstract translation: 本发明使用大的表面体积比的材料用于分离，剥离层和牺牲材料应用。 本发明概述了材料概念，应用设计和制造方法。 本发明使用沉积柱/空隙网络材料作为大表面积与体积比的材料的实例进行了说明。 在讨论的许多具体应用中，显示了在母基板上的层压体上产生结构，然后使用分离层材料方法，使用本分离方案将该层压体与母基板分开是有利的。 还显示出本发明材料具有优异的脱模层效用。 在许多应用中，还显示了该方法如何用于在各种基底中或其上独特地形成腔，通道，气隙和相关结构。 此外，证明了将空腔形成方案与层压分离方案组合也是有可能和有利的。

公开(公告)号：WO01080286A2

公开(公告)日：2001-10-25

申请号：PCT/US2001/012281

申请日：2001-04-17

IPC: B81B3/00 ,  B81C1/00 ,  C23C16/24 ,  C23C16/511 ,  H01L21/306 ,  H01M8/02 ,  H01L

CPC classification number: B81C1/0038 ,  B81C99/008 ,  B81C2201/0109 ,  B81C2201/0115 ,  B81C2203/0127 ,  C23C16/24 ,  C23C16/511

Abstract: This invention uses large surface to volume ratio materials for separation, release layer, and sacrificial material applications. The invention outlines the material concept, application designs, and fabrication methodologies. The invention is demonstrated using deposited column/void network materials as examples of large surface to volume ratio materials. In a number of the specific applications discussed, it is shown that it is advantageous to create structures on a laminate on a mother substrate and then, using the separation layer material approach, to separate this laminate from the mother substrate using the present separation scheme. It is also shown that the present materials have excellent release layer utility. In a number of applications it is also shown how the approach can be used to uniquely form cavities, channels, air-gaps, and related structures in or on various substrates. Further, it is demonstrated that it also can be possible and advantageous to combine the schemes for cavity formation with the scheme for laminate separation.

Abstract translation: 本发明使用大的表面体积比的材料用于分离，剥离层和牺牲材料应用。 本发明概述了材料概念，应用设计和制造方法。 本发明使用沉积柱/空隙网络材料作为大表面积与体积比的材料的实例进行了说明。 在讨论的许多具体应用中，显示了在母基板上的层压体上产生结构，然后使用分离层材料方法，使用本分离方案将该层压体与母基板分离是有利的。 还显示出本发明材料具有优异的脱模层效用。 在许多应用中，还显示了该方法如何用于在各种基底中或其上独特地形成腔，通道，气隙和相关结构。 此外，证明了将空腔形成方案与层压分离方案组合也是有可能和有利的。

公开(公告)号：US20190013151A1

公开(公告)日：2019-01-10

申请号：US15803155

申请日：2017-11-03

Applicant: Honeywell International Inc.

Inventor： Steven Tin ,  Neil Krueger

IPC: H01G7/02 ,  H02N1/08 ,  B81C1/00 ,  H04B1/04

CPC classification number: H01G7/025 ,  B81C1/00515 ,  B81C2201/0114 ,  B81C2201/0115 ,  H02N1/08 ,  H04B1/04

Abstract: An ultra-high charge density electret is disclosed. The ultra-high charge density electret includes a three-dimensional structure having a plurality of sidewalls. A porous silicon dioxide film is formed on the plurality of sidewalls, and the porous silicon dioxide film is charged with a plurality of positive or negative ions.

公开(公告)号：US10053360B1

公开(公告)日：2018-08-21

申请号：US15685879

申请日：2017-08-24

Applicant: Kionix, Inc.

Inventor： Martin Heller

IPC: H01L21/00 ,  B81C1/00

CPC classification number: B81C1/00047 ,  B81C1/00095 ,  B81C2201/0109 ,  B81C2201/0115 ,  B81C2201/0132 ,  B81C2201/0171 ,  B81C2201/0178

Abstract: A method of processing a semiconductor substrate having a first conductivity type includes, in part, forming a first implant region of a second conductivity type in the semiconductor substrate where the first implant region is characterized by a first depth, forming a second implant region of the first conductivity type in the semiconductor substrate where the second implant region is characterized by a second depth smaller than the first depth, forming a porous layer within the semiconductor substrate where the porous layer is adjacent the first implant region, and growing an epitaxial layer on the semiconductor substrate thereby causing the porous layer to collapse and form a cavity.

公开(公告)号：US20180208459A1

公开(公告)日：2018-07-26

申请号：US15875635

申请日：2018-01-19

Applicant: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.

Inventor： Sabine TRUPP ,  Michael HENFLING ,  Karl NEUMEIER

IPC: B81C1/00

CPC classification number: B81C1/00206 ,  B81B2201/0214 ,  B81C2201/0114 ,  B81C2201/0115 ,  B81C2201/016 ,  G01N27/128 ,  G01N33/0027 ,  Y02P70/521

Abstract: A method of producing a semiconductor device includes providing a carrier structure having a semiconductor substrate; applying or introducing a precursor substance onto or into the carrier structure, treating the precursor substance for producing a porous matrix structure; introducing a functionalization substance into the porous matrix structure.

公开(公告)号：US09880036B2

公开(公告)日：2018-01-30

申请号：US14933982

申请日：2015-11-05

Applicant: Xiang Zheng Tu

Inventor： Xiang Zheng Tu

IPC: G01F1/692 ,  B81C1/00 ,  H01L35/34 ,  G01F1/684 ,  G01F1/688 ,  H01L21/3063

CPC classification number: G01F1/692 ,  B81C1/00158 ,  B81C1/00246 ,  B81C1/00571 ,  B81C2201/0115 ,  B81C2201/0142 ,  G01F1/6845 ,  G01F1/688 ,  H01L21/3063 ,  H01L35/34

Abstract: A vacuum-cavity-insulated flow sensor and related fabrication method are described. The sensor comprises a porous silicon wall with numerous vacuum-pores which is created in a silicon substrate, a porous silicon membrane with numerous vacuum-pores which is surrounded and supported by the porous silicon wall, and a cavity with a vacuum-space which is disposed beneath the porous silicon membrane and surrounded by the porous silicon wall. The fabrication method includes porous silicon formation and silicon polishing in HF solution.