公开(公告)号：US09724869B2

公开(公告)日：2017-08-08

申请号：US14583940

申请日：2014-12-29

Applicant: TactoTek Oy

Inventor： Paavo Niskala ,  Jarmo Saaski ,  Pasi Raappana ,  Mikko Heikkinen ,  Mikko Sippari ,  Jarkko Torvinen ,  Antti Keranen

IPC: H05K1/00 ,  B29C51/14 ,  H05K1/18 ,  G06F1/16 ,  H05K3/00 ,  B29L31/34 ,  B29C51/16

CPC classification number: B29C51/14 ,  B29C51/16 ,  B29L2031/3406 ,  B29L2031/3425 ,  B29L2031/3431 ,  B29L2031/3481 ,  G06F1/163 ,  G06F1/1652 ,  G06F1/1658 ,  H05K1/0266 ,  H05K1/0284 ,  H05K1/185 ,  H05K1/189 ,  H05K3/0014 ,  H05K3/284 ,  H05K2201/0108 ,  H05K2201/0133 ,  H05K2201/0145 ,  H05K2201/0154 ,  H05K2201/09118 ,  H05K2201/10545 ,  H05K2203/1311 ,  H05K2203/1316

Abstract: Multilayer structure (200) for electronic devices, including a flexible substrate film (102) for accommodating electronics, a number of electrical elements (204, 206) provided to the flexible substrate film, preferably by element of printed electronics and/or surface mounting, a protective layer (104) laminated onto at least first surface of the substrate film, the protective layer being configured to mask perceivable physical deviation of the substrate, such as uneven surface profile or coloring, substantially at the location of the number of elements, from outside perception, optionally visual perception and/or tactile inspection taking place via the protective layer, and plastic layer (106) molded over at least second surface of the substrate film opposite to the first surface. A corresponding method of manufacture is presented.

公开(公告)号：US09723711B2

公开(公告)日：2017-08-01

申请号：US14819040

申请日：2015-08-05

Applicant: MC10, Inc.

Inventor： Brian David Elolampi ,  Roozbeh Ghaffari ,  Bassel de Graff ,  William J. Arora ,  Xiaolong Hu

IPC: H05K1/02 ,  H01L21/683 ,  H05K3/46 ,  H05K3/06 ,  H05K1/11 ,  H05K1/03 ,  H01L23/13 ,  H01L25/065 ,  H01L25/07 ,  H01L25/00 ,  H01L23/498 ,  H01L23/538

CPC classification number: H05K1/0278 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/4985 ,  H01L23/5389 ,  H01L25/0655 ,  H01L25/072 ,  H01L25/50 ,  H01L2221/68318 ,  H01L2221/6835 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2224/24137 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/1461 ,  H05K1/0326 ,  H05K1/0346 ,  H05K1/115 ,  H05K3/067 ,  H05K3/4644 ,  H05K2201/0141 ,  H05K2201/0145 ,  H05K2201/0154 ,  H01L2924/00

Abstract: Flexible electronic structure and methods for fabricating flexible electronic structures are provided. An example method includes applying a first layer to a substrate, creating a plurality of vias through the first layer to the substrate, and applying a second polymer layer to the first layer such that the second polymer forms anchors contacting at least a portion of the substrate. At least one electronic device layer is disposed on a portion of the second polymer layer. At least one trench is formed through the second polymer layer to expose at least a portion of the first layer. At least a portion of the first layer is removed by exposing the structure to a selective etchant to providing a flexible electronic structure that is in contact with the substrate. The electronic structure can be released from the substrate.

公开(公告)号：US20170207156A1

公开(公告)日：2017-07-20

申请号：US15475133

申请日：2017-03-31

Applicant: Subtron Technology Co., Ltd.

Inventor： Chao-Min Wang

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/683 ,  H01L23/13

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/49838 ,  H01L23/49866 ,  H01L2221/68345 ,  H01L2221/68381 ,  H05K1/0296 ,  H05K1/0298 ,  H05K1/09 ,  H05K3/0058 ,  H05K3/0061 ,  H05K3/048 ,  H05K3/06 ,  H05K3/064 ,  H05K3/14 ,  H05K3/4652 ,  H05K3/4682 ,  H05K2201/0145 ,  H05K2203/0152 ,  H05K2203/0502 ,  H05K2203/0548 ,  H05K2203/066

Abstract: A substrate structure includes a dielectric layer, a metal foil, a patterned metal layer, a first patterned solder-resist layer, a release layer and a second patterned solder-resist layer. The dielectric layer includes a first surface having a plurality of recesses and a second surface. The metal foil is disposed on the second surface. The patterned metal layer is disposed on the first surface, the patterned metal layer has a plurality of openings, and the openings are respectively corresponding to and expose the recesses. The first patterned solder-resist layer is filled in each of the recesses and corresponding to each of the openings. A top surface of the first patterned solder-resist layer is substantially coplanar with a top surface of the patterned metal layer. The second patterned solder-resist layer is disposed on the first patterned solder-resist layer and in the openings, and covers a portion of the patterned metal layer.

公开(公告)号：US09648760B2

公开(公告)日：2017-05-09

申请号：US15052885

申请日：2016-02-25

Applicant: Subtron Technology Co., Ltd.

Inventor： Chao-Min Wang

IPC: H05K3/06 ,  H05K1/09 ,  H05K3/46 ,  H05K1/02 ,  H05K3/14 ,  H05K3/00 ,  H05K3/04

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/49838 ,  H01L23/49866 ,  H01L2221/68345 ,  H01L2221/68381 ,  H05K1/0296 ,  H05K1/0298 ,  H05K1/09 ,  H05K3/0058 ,  H05K3/0061 ,  H05K3/048 ,  H05K3/06 ,  H05K3/064 ,  H05K3/14 ,  H05K3/4652 ,  H05K3/4682 ,  H05K2201/0145 ,  H05K2203/0152 ,  H05K2203/0502 ,  H05K2203/0548 ,  H05K2203/066

Abstract: A substrate structure includes a dielectric layer, a metal foil, a patterned metal layer, a first patterned solder-resist layer and a second patterned solder-resist layer. The dielectric layer includes a first surface and a second surface, and the first surface has a plurality of recesses. The metal foil is disposed on the second surface. The patterned metal layer is disposed on the first surface, the patterned metal layer has a plurality of openings, and the openings are respectively corresponding to and expose the recesses. The first patterned solder-resist layer is filled in each of the recesses and corresponding to each of the openings. A top surface of the first patterned solder-resist layer is substantially coplanar with a top surface of the patterned metal layer. The second patterned solder-resist layer is disposed on the first patterned solder-resist layer and in the openings, and covers a portion of the patterned metal layer.

公开(公告)号：US09628652B2

公开(公告)日：2017-04-18

申请号：US15093813

申请日：2016-04-08

Applicant: KONICA MINOLTA, INC.

Inventor： Kiyohito Tsujihara ,  Shiro Umeda ,  Yuki Higuchi

IPC: H04N1/00 ,  H04N1/04 ,  H05K1/00

CPC classification number: H04N1/0083 ,  H04N1/00795 ,  H04N1/04 ,  H04N2201/0049 ,  H04N2201/0081 ,  H05K1/00 ,  H05K1/0281 ,  H05K1/147 ,  H05K2201/0145 ,  H05K2201/2009

Abstract: An image reading device which reads an image to obtain an image signal includes: a scanning unit; a chassis member; a control unit provided in a position which does not move together with the scanning unit; and a flexible flat cable which connects the scanning unit to the control unit, includes one end attached to a side of the chassis member and a position other than the one end fixed to a position which does not move with the scanning unit, includes a range closer to the one end than the fixed position parallel to a moving direction of the scanning unit, and is arranged to extend from the one end to one side, be bent into a U-shape, enter between the scanning unit and the chassis member, and reach the fixed position, and the flexible flat cable includes a transmitting layer, a shielding layer, and a stress adjusting layer.

公开(公告)号：US20170105283A1

公开(公告)日：2017-04-13

申请号：US15179513

申请日：2016-06-10

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Ho Yoon KIM ,  Kyoung Jin JUN ,  Min Kyoung CHEON

IPC: H05K1/02 ,  H05K1/03 ,  H05K1/14 ,  H05K1/18 ,  H05K1/11

CPC classification number: H05K1/0271 ,  H05K1/0306 ,  H05K1/032 ,  H05K1/0346 ,  H05K1/0393 ,  H05K1/111 ,  H05K1/141 ,  H05K1/181 ,  H05K1/189 ,  H05K3/301 ,  H05K3/3442 ,  H05K2201/0145 ,  H05K2201/0154 ,  H05K2201/041 ,  H05K2201/049 ,  H05K2201/2045 ,  Y02P70/613

Abstract: An electronic component includes a body including a dielectric material and internal electrodes embedded in the dielectric material; external electrodes connected to the internal electrodes and disposed on the body; a first substrate connected to the external electrodes and disposed on one side of the body; and a second substrate connected to the first substrate and disposed on one side of the first substrate. The first and second substrates have different Young's modulus.

公开(公告)号：US09591746B2

公开(公告)日：2017-03-07

申请号：US15199913

申请日：2016-06-30

Applicant: Industrial Technology Research Institute

Inventor： Wei-Yuan Cheng ,  Chen-Chu Tsai ,  Yuh-Zheng Lee

IPC: H05K1/00 ,  H05K3/00 ,  H05K1/02 ,  H01L23/498 ,  H01L23/31 ,  H01L21/683 ,  H05K1/11 ,  H05K3/40

CPC classification number: H05K1/028 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/4985 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/16 ,  H01L2924/181 ,  H05K1/0281 ,  H05K1/115 ,  H05K3/0032 ,  H05K3/007 ,  H05K3/4038 ,  H05K2201/0145 ,  H05K2201/0154 ,  H05K2201/10106 ,  H05K2201/10128 ,  H05K2201/2009 ,  H05K2203/1178 ,  H01L2924/00012

Abstract: According to embodiments of the disclosure, an electronic device package may include a wire layer and a rigid element. The wire layer includes a first surface and a second surface opposite to each other, and the second surface of the wire layer has at least one coarse structure. A portion of the second surface having the coarse structure has a greater roughness than another portion of the second surface. The rigid element is disposed on the first surface of the wire layer, wherein a stiffness of the rigid element is greater than a stiffness of the wire layer and a projection area of the coarse structure on the first surface of the wire layer overlaps an edge of the rigid element.

Abstract translation: 根据本公开的实施例，电子设备封装可以包括导线层和刚性元件。 线层包括彼此相对的第一表面和第二表面，并且线层的第二表面具有至少一个粗糙结构。 具有粗糙结构的第二表面的一部分具有比第二表面的另一部分更大的粗糙度。 刚性元件设置在线层的第一表面上，其中刚性元件的刚度大于金属丝层的刚度，并且粗糙结构在金属丝层的第一表面上的投影区域与 刚性元素。

公开(公告)号：US20170042019A1

公开(公告)日：2017-02-09

申请号：US14820201

申请日：2015-08-06

Applicant: International Business Machines Corporation

Inventor： Matthew S. Doyle ,  Joseph Kuczynski ,  Kevin M. O'Connell ,  Chelsie M. Peterson ,  Mark D. Plucinski ,  Timothy J. Tofil

IPC: H05K1/02 ,  H05K1/09 ,  H05K1/03 ,  H05K1/18

CPC classification number: H05K1/0275 ,  H05K1/0213 ,  H05K1/0274 ,  H05K1/03 ,  H05K1/09 ,  H05K1/097 ,  H05K1/18 ,  H05K3/143 ,  H05K2201/0108 ,  H05K2201/0145 ,  H05K2201/0323 ,  H05K2201/0332

Abstract: In an example, a polymeric material is disclosed. The polymeric material includes a polymer substrate and a plurality of graphene traces arranged to form a tamper detection circuit on the polymer substrate.

Abstract translation: 在一个实例中，公开了聚合物材料。 聚合物材料包括聚合物基底和布置成在聚合物基底上形成篡改检测电路的多个石墨烯迹线。

公开(公告)号：US20170006701A1

公开(公告)日：2017-01-05

申请号：US15125573

申请日：2014-03-11

Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

Inventor： Vincenzo CASASANTA, III

IPC: H05K1/03 ,  H05K1/11 ,  H05K1/18 ,  H05K3/40 ,  H05K3/12 ,  C08J5/04 ,  B32B5/12 ,  B32B27/08 ,  B32B27/18 ,  B32B27/22 ,  B32B27/36 ,  C08J5/00 ,  H05K1/09 ,  H05K3/00

CPC classification number: H05K1/0366 ,  B32B3/266 ,  B32B5/02 ,  B32B5/08 ,  B32B5/12 ,  B32B5/22 ,  B32B5/26 ,  B32B9/02 ,  B32B9/04 ,  B32B25/02 ,  B32B25/042 ,  B32B25/08 ,  B32B27/08 ,  B32B27/18 ,  B32B27/22 ,  B32B27/28 ,  B32B27/281 ,  B32B27/283 ,  B32B27/285 ,  B32B27/286 ,  B32B27/302 ,  B32B27/304 ,  B32B27/306 ,  B32B27/308 ,  B32B27/32 ,  B32B27/34 ,  B32B27/36 ,  B32B27/365 ,  B32B27/38 ,  B32B27/40 ,  B32B27/42 ,  B32B2260/021 ,  B32B2260/04 ,  B32B2260/046 ,  B32B2262/04 ,  B32B2262/062 ,  B32B2262/065 ,  B32B2262/10 ,  B32B2262/101 ,  B32B2262/14 ,  B32B2264/0278 ,  B32B2264/105 ,  B32B2270/00 ,  B32B2307/202 ,  B32B2307/546 ,  B32B2307/7163 ,  B32B2307/75 ,  B32B2457/08 ,  C08J5/005 ,  C08J5/041 ,  C08J2367/04 ,  C08K3/08 ,  C08K2003/0806 ,  H05K1/0353 ,  H05K1/036 ,  H05K1/0393 ,  H05K1/095 ,  H05K1/097 ,  H05K1/115 ,  H05K1/181 ,  H05K3/0011 ,  H05K3/1216 ,  H05K3/1241 ,  H05K3/125 ,  H05K3/1275 ,  H05K3/22 ,  H05K3/4038 ,  H05K2201/012 ,  H05K2201/0133 ,  H05K2201/0145 ,  H05K2201/0162 ,  H05K2201/0212 ,  H05K2201/0251 ,  H05K2201/0269 ,  H05K2201/0278 ,  H05K2201/0284 ,  H05K2201/0293 ,  H05K2203/0271 ,  H05K2203/0769 ,  H05K2203/1105 ,  H05K2203/176 ,  H05K2203/178 ,  Y02P70/611 ,  Y02P70/613 ,  C08L67/04

Abstract: Biodegradable printed circuit boards, or PCBs, may be produced from substrate sheets that include at least one biodegradable polymer. In addition, the electrical traces used on the PCBs, may also include a biodegradable polymer incorporated with an electrically conductive material. The PCBs may be composted to degrade the PCBs, and the

Abstract translation: 可生物降解的印刷电路板或PCB可以由包括至少一种可生物降解的聚合物的基材片制成。 另外，PCB上使用的电迹线也可以包括结合有导电材料的可生物降解的聚合物。 PCB可能被堆肥以降解PCBs

公开(公告)号：US20160219763A1

公开(公告)日：2016-07-28

申请号：US15005443

申请日：2016-01-25

Applicant: Michael A. TISCHLER ,  Calvin Wade SHEEN

Inventor： Michael A. TISCHLER ,  Calvin Wade SHEEN

IPC: H05K13/04 ,  C22B7/00

CPC classification number: C22B7/005 ,  H05K1/189 ,  H05K3/043 ,  H05K13/0486 ,  H05K2201/0145 ,  H05K2201/10106 ,  H05K2203/0108 ,  H05K2203/0195 ,  H05K2203/1545 ,  H05K2203/178

Abstract: In accordance with certain embodiments, devices are recycled by removing one or more electronic components from a portion of the device and urging one or more regions of the portion of the device toward an abrasion head. The abrasion head mechanically removes at least a portion of patternable material in each of the one or more regions. The steps are repeated for subsequent portions of the device.

Abstract translation: 根据某些实施例，通过从装置的一部分移除一个或多个电子部件并将装置的一个或多个区域推向磨损头来再循环装置。 磨损头在一个或多个区域的每一个中机械地去除至少一部分可图案材料。 对于设备的后续部分重复这些步骤。