公开(公告)号：EP1314172B8

公开(公告)日：2005-06-15

申请号：EP01960431.3

申请日：2001-06-30

Applicant: Moeller GmbH

Inventor： SCHMITZ, Gerd

IPC: H01C17/065

CPC classification number: H05K1/167 ,  H01C17/0652 ,  H05K1/0257 ,  H05K1/095 ,  H05K3/386 ,  H05K2201/0323 ,  H05K2201/09881 ,  H05K2203/1453 ,  Y10T29/49099

Abstract: The invention relates to an electronic assembly, in particular, for low power consumption electric switching devices such as low power contactors, time relays or the like. In order to provide protection against input current pulses, an ohmic resistor (6) is provided in the form of a resistive layer that is applied by pressing.

公开(公告)号：EP1471167A3

公开(公告)日：2005-02-02

申请号：EP04252270.6

申请日：2004-04-16

Applicant: Shinko Electric Industries Co., Ltd.

Inventor： Murayama, Kei Shinko Electric Industries Co., Ltd.

IPC: C23C18/16 ,  C23C18/28

CPC classification number: H05K3/244 ,  C23C18/1605 ,  C23C18/1608 ,  C23C18/1635 ,  C23C18/1651 ,  C23C18/1889 ,  C23C18/208 ,  C23C18/285 ,  C23C18/30 ,  C23C18/36 ,  H05K2201/0761 ,  H05K2201/09881 ,  H05K2203/013 ,  H05K2203/0716 ,  H05K2203/072 ,  H05K2203/0796

Abstract: An electroless plating method of the present invention includes the steps of preparing a substrate (15) having an insulating body (10) and a conductive pattern (12) formed thereon, adhering a catalytic metal (14) serving as a catalyst of an electroless plating onto the insulating body (10) and the conductive pattern (12), forming selectively a protection film (16) or an oxidizing agent used to oxidize the catalytic metal on the catalytic metal (14) in a space portion (S) between the conductive pattern (12), and forming selectively a metal layer (18) on the conductive pattern (12) by the electroless plating.

公开(公告)号：EP0923094A3

公开(公告)日：2004-04-14

申请号：EP98122945.3

申请日：1998-12-03

Applicant: TDK Corporation

Inventor： Tokuoka, Yasumichi ,  Nomura, Takeshi

IPC: H01G4/30

CPC classification number: H05K3/4667 ,  H01G4/30 ,  H01G4/308 ,  H05K1/0306 ,  H05K3/046 ,  H05K2201/09881 ,  H05K2203/0108 ,  H05K2203/0528 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49126 ,  Y10T29/49128

Abstract: Internal electrode layers of a multilayer ceramic electronic element are structured such that spaces, which are formed between adjacent internal electrodes, are eliminated so as to substantially flatten the internal electrode layers. Moreover, the thickness of each green dielectric layer is reduced. To achieve this, a laminating process is performed by a thermal transfer printing method such that a thermal transfer conductor material and a thermal transfer dielectric material are used so as to form internal electrode portions and green dielectric portions. Thus, the internal electrode layers are formed.

公开(公告)号：EP1194022A4

公开(公告)日：2004-03-17

申请号：EP00931571

申请日：2000-05-25

Applicant: IBIDEN CO LTD

Inventor： ASAI MOTOO ,  WANG DONGDONG ,  MORI TAKAHIRO

IPC: H01L21/48 ,  H01L23/498 ,  H05K1/03 ,  H05K3/00 ,  H05K3/10 ,  H05K3/18 ,  H05K3/38 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K3/423 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/036 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/181 ,  H05K3/381 ,  H05K3/385 ,  H05K3/387 ,  H05K3/388 ,  H05K3/426 ,  H05K3/427 ,  H05K3/4602 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09736 ,  H05K2201/09881 ,  H05K2203/0315 ,  H05K2203/0733 ,  H05K2203/0773 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/05599

Abstract: A multilayer printed wiring board in which the strength is ensured by sandwiching a metal layer (18) between insulating layers (14, 20), thereby a core sheet (30) can be thin, and the thickness of the multilayer printed wiring board is reduced. Moreover, since a blind hole (22) extending to the metal layer (18) is formed only in insulating layers (14, 20), the fine blind hole (22) can easily be made by a laser beam, and a through hole (36) having a small diameter can be formed.

公开(公告)号：EP1395102A2

公开(公告)日：2004-03-03

申请号：EP03018683.7

申请日：2003-08-22

Applicant: Kuraray Co., Ltd.

Inventor： Tsugaru, Toshinori, Kuraray Co., Ltd. ,  Sunamoto, Tatsuya, Kuraray Co., Ltd. ,  Yoshikawa, Tadao, Kuraray Co., Ltd.

IPC: H05K3/46

CPC classification number: H05K3/4655 ,  H05K3/386 ,  H05K3/4069 ,  H05K3/4617 ,  H05K3/4626 ,  H05K3/4652 ,  H05K2201/0129 ,  H05K2201/0141 ,  H05K2201/0195 ,  H05K2201/09881 ,  H05K2203/1189 ,  Y10T428/24917

Abstract: To provide a simplified method of making a multi-layer circuit board capable of observing a high density surface mounting of electronic parts, a method is provided for making a multi-layer circuit board including a first film (A) and at least two more films, second and third films (B and C), each being made of thermoplastic polymer capable of forming an optically anisotropic melt phase. The first film (A) has a low melting point (Tm 1 ), and the second and third films (B and C) have respective melting points (Tm 2 B and Tm 2 C) higher than the melting point (Tm 1 ) of the first film (A). And at least one of the second and the third films have a circuit pattern thereon. The first to third films (A to C) are thermo compressed together with the first film (A) interposed between the second and third films (B and C). The method includes causing at least one of the circuit patterns (D) on one of the second and third films (B and C) to contact an opposing surface of the other of the second and third films (B and C) through the first film (A) during the thermo compression bonding of the first to third films (A to C).

Abstract translation: 为了提供能够观察电子部件的高密度表面安装的多层电路板的简化方法，提供了一种制造包括第一膜（A）和至少两个以上膜的多层电路板的方法 ，第二和第三膜（B和C），每个由能够形成光学各向异性熔融相的热塑性聚合物制成。 第一膜（A）具有低熔点（Tm 1），第二膜和第三膜（B和C）的熔点（Tm 2 B和Tm 2 C）分别比熔点 第一部电影（A）。 并且第二和第三薄膜中的至少一个具有其上的电路图案。 第一至第三膜（A至C）与介于第二和第三膜（B和C）之间的第一膜（A）一起被热压。 所述方法包括使所述第二和第三膜（B和C）中的一个上的电路图案（D）中的至少一个与所述第二和第三膜（B和C）中的另一个的相对表面通过所述第一膜 （A）在第一至第三膜（A至C）的热压接期间。

公开(公告)号：EP1387369A1

公开(公告)日：2004-02-04

申请号：EP02724688.3

申请日：2002-05-02

Applicant: Sony Corporation

Inventor： KOSEMURA, Takahiko, c/o SONY CORPORATION ,  OKUBORA, Akihiko, c/o SONY CORPORATION ,  HIRABAYASHI, Takayuki, c/o SONY CORPORATION ,  OGINO, Tatsuya, c/o SONY CORPORATION ,  HAYASHI, Kuniyuki, Sony Semiconductor Kyushu Co.

IPC: H01F17/00 ,  H05K3/46

CPC classification number: H01L23/66 ,  H01F17/0006 ,  H01L23/49822 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01087 ,  H05K1/165 ,  H05K3/4602 ,  H05K3/4664 ,  H05K3/467 ,  H05K2201/0195 ,  H05K2201/09881

Abstract: The present invention provides a high-frequency module configuring a micro communication functional module, which includes a base substrate (2) which has multiple pattern wiring layers (6a) (6b) (9a) (9b) and dielectric insulating layers (5) (8) (11) formed therein, and has a buildup surface for smoothing the upper layer thereof, and a high-frequency element layer (4) formed on the buildup surface, which has an inductor (20) formed therein via an insulating layer (19) formed on the buildup surface. The base substrate (2) is provided with a region (30) where the pattern wiring layers (6a) (6b) (9a) (9b) are not formed from the upper layer to at least the mid portion thereof along the thickness direction, and the inductor (20) of the high-frequency element layer (4) is formed directly above the region (30).

Abstract translation: 本发明提供一种配置微通信功能模块的高频模块，其包括具有多个图案布线层（6a）（6b）（9a）（9b）和介电绝缘层（5）的基底（2） 8）（11），并且具有用于使其上层平滑的累积表面和形成在积累表面上的高频元件层（4），该高频元件层（4）具有经由绝缘层形成在其中的电感器（20） 19）形成在堆积表面上。 基底基板（2）具有区域（30），其中图案布线层（6a）（6b）（9a）（9b））不沿着厚度方向至少至少其中间部分形成， 并且高频元件层（4）的电感器（20）直接形成在区域（30）的上方。

公开(公告)号：EP1194022A1

公开(公告)日：2002-04-03

申请号：EP00931571.4

申请日：2000-05-25

Applicant: IBIDEN CO., LTD.

Inventor： ASAI, Motoo, Ogaki-kita-kojou, Ibiden Co., Ltd. ,  WANG, Dongdong, Ogaki-kita-kojou, Ibiden Co., Ltd. ,  MORI, Takahiro, Ogaki-kita-kojou, Ibiden Co., Ltd.

IPC: H05K3/46

CPC classification number: H05K3/423 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/036 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/181 ,  H05K3/381 ,  H05K3/385 ,  H05K3/387 ,  H05K3/388 ,  H05K3/426 ,  H05K3/427 ,  H05K3/4602 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09736 ,  H05K2201/09881 ,  H05K2203/0315 ,  H05K2203/0733 ,  H05K2203/0773 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/05599

Abstract: A metal layer 18 is sandwiched between insulating layers 14 and 20 so that required strength is maintained. Hence it follows that the thickness of a core substrate 30 can be reduced and, therefore, the thickness of a multi-layer printed circuit board can be reduced. Formation of non-penetrating openings 22 which reach the metal layer 18 in the insulating layers 14 and 20 is simply required. Therefore, small non-penetrating openings 22 can easily be formed by applying laser beams. Thus, through holes 36 each having a small diameter can be formed.

公开(公告)号：EP1121008A1

公开(公告)日：2001-08-01

申请号：EP99933214.1

申请日：1999-07-30

Applicant: IBIDEN CO., LTD.

Inventor： HIROSE, Naohiro ,  NODA, Kouta ,  SEGAWA, Hiroshi ,  EN, Honjin ,  TSUKADA, Kiyotaka ,  ISHIDA, Naoto ,  ASANO, Kouji ,  SHOUDA, Atsushi

IPC: H05K3/46

CPC classification number: H05K3/4652 ,  B23K26/389 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0201 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0055 ,  H05K3/0094 ,  H05K3/108 ,  H05K3/28 ,  H05K3/381 ,  H05K3/383 ,  H05K3/384 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4661 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0358 ,  H05K2201/062 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2201/09881 ,  H05K2203/0307 ,  H05K2203/0353 ,  H05K2203/0554 ,  H05K2203/0773 ,  H05K2203/107 ,  H05K2203/121 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: An opening is formed in resin 20 by a laser beam so that a via hole is formed. At this time, copper foil 22, the thickness of which is reduced (to 3 µ m) by performing etching to lower the thermal conductivity is used as a conformal mask. Therefore, an opening 20a can be formed in the resin 20 if the number of irradiation of pulse-shape laser beam is reduced. Therefore, occurrence of undercut of the resin 20 which forms an interlayer insulating resin layer can be prevented. Thus, the reliability of the connection of the via holes can be improved.

Abstract translation: 通过激光束在树脂20中形成开口，从而形成通孔。 此时，通过执行蚀刻以降低热导率来减小厚度（至3μm）的铜箔22被用作共形掩模。 因此，如果减少脉冲形状激光束的照射次数，则可以在树脂20中形成开口20a。 因此，可以防止形成层间绝缘树脂层的树脂20发生底切。 因此，可以提高通孔连接的可靠性。

公开(公告)号：EP1112672A1

公开(公告)日：2001-07-04

申请号：EP99938904.2

申请日：1999-07-30

Applicant: Kulicke & Soffa Holdings, Inc.

Inventor： STRANDBERG, Jan, I. ,  CHAZAN, David, J. ,  SKINNER, Michael, P.

IPC: H05K1/03

CPC classification number: H05K1/0271 ,  H01L21/481 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5385 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/3011 ,  H05K3/0023 ,  H05K3/0032 ,  H05K3/4602 ,  H05K3/4644 ,  H05K3/4673 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/068 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09781 ,  H05K2201/098 ,  H05K2201/09881 ,  H05K2203/0353 ,  H05K2203/0585 ,  H05K2203/0759 ,  H05K2203/1476 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05644 ,  H01L2224/05647

Abstract: Low-impedance high-density deposited-on-laminate (DONL) structures having reduced stress features reducing metallization present on the laminate printed circuit board. In this manner, reduced is the force per unit area exerted on the dielectric material disposed adjacent to the laminate material that is typically present during thermal cycling of the structure.

公开(公告)号：EP0923094A2

公开(公告)日：1999-06-16

申请号：EP98122945.3

申请日：1998-12-03

Applicant: TDK Corporation

Inventor： Tokuoka, Yasumichi ,  Nomura, Takeshi

IPC: H01G4/30

CPC classification number: H05K3/4667 ,  H01G4/30 ,  H01G4/308 ,  H05K1/0306 ,  H05K3/046 ,  H05K2201/09881 ,  H05K2203/0108 ,  H05K2203/0528 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49126 ,  Y10T29/49128

Abstract: Internal electrode layers of a multilayer ceramic electronic element are structured such that spaces, which are formed between adjacent internal electrodes, are eliminated so as to substantially flatten the internal electrode layers. Moreover, the thickness of each green dielectric layer is reduced. To achieve this, a laminating process is performed by a thermal transfer printing method such that a thermal transfer conductor material and a thermal transfer dielectric material are used so as to form internal electrode portions and green dielectric portions. Thus, the internal electrode layers are formed.

Abstract translation: 多层陶瓷电子元件的内部电极层被构造为使得在相邻的内部电极之间形成的空间被消除，以使内部电极层基本平坦化。 此外，每个绿色介电层的厚度减小。 为了实现这一点，通过使用热转印导体材料和热转印介电材料以形成内部电极部分和绿色电介质部分的热转印打印方法进行层压工艺。 因此，形成内部电极层。