公开(公告)号：EP4369408A1

公开(公告)日：2024-05-15

申请号：EP23198686.0

申请日：2023-09-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： PANDEY, Shesh M. ,  KRISHNASAMY, Rajendran ,  HOLT, Judson R. ,  TAN, Chung Foong

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L29/407 ,  H01L29/0653 ,  H01L29/7835 ,  H01L29/404

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a transistor with a metal field plate contact and methods of manufacture. The structure includes: a gate structure (14) on a semiconductor substrate (12); a shallow trench isolation structure (18) within the semiconductor substrate; and a contact (22) extending from the gate structure and into the shallow trench isolation structure.

公开(公告)号：EP4312479A1

公开(公告)日：2024-01-31

申请号：EP23179651.7

申请日：2023-06-16

Applicant: GlobalFoundries U.S. Inc.

Inventor： GOPINATH, Venkatesh ,  PAUL, Bipul C. ,  HU, Xiaoli

IPC: H10B63/00

Abstract: Structures that include resistive memory elements and methods of forming a structure that includes resistive memory elements. The structure comprises a first plurality of resistive memory elements including a first plurality of bottom electrodes, a first top electrode, and a first switching layer between the first top electrode and the first plurality of bottom electrodes. The structure further comprises a second plurality of resistive memory elements including a second plurality of bottom electrodes, a second top electrode, and a second switching layer between the second top electrode and the second plurality of bottom electrodes. The first top electrode is shared by the first plurality of resistive memory elements, and the second top electrode is shared by the second plurality of resistive memory elements.

公开(公告)号：EP4307375A1

公开(公告)日：2024-01-17

申请号：EP23179101.3

申请日：2023-06-14

Applicant: GlobalFoundries U.S. Inc.

Inventor： TESTA, Paolo Valerio ,  SYED, Shafiullah

IPC: H01L27/06 ,  H01L27/07 ,  H01L23/522 ,  H03F3/195 ,  H01L29/92

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a common-gate amplifier circuit and methods of operation. The structure includes at least one well in a substrate, a first metal layer connected to a gate of a transistor circuit, a second metal layer overlapped over the first metal layer to form a capacitor (C3, C4), and a third metal layer connected with vias to the first metal layer and overlapped with the second metal layer to form a second capacitor (C1, C2). At least one capacitance (C5, C6, C7, C8) in at least one of a junction between the at least one well and the substrate and between overlapped metal layers of the first metal layer, the second metal layer, and the third metal layer.

公开(公告)号：EP4296735A1

公开(公告)日：2023-12-27

申请号：EP22206329.9

申请日：2022-11-09

Applicant: GlobalFoundries U.S. Inc.

Inventor： Bian, Yusheng

IPC: G02B6/126

Abstract: A structure comprising a first waveguide with first end sections and a first coupling section between the first end sections, wherein the first waveguide comprises a first core; and a second waveguide having second end sections and a second coupling section between the second end sections and adjacent to the first coupling section, wherein the second waveguide comprises a second core positioned laterally adjacent to the first core; and at least one additional second core stacked vertically with the second core.

公开(公告)号：EP4290284A1

公开(公告)日：2023-12-13

申请号：EP22201113.2

申请日：2022-10-12

Applicant: GlobalFoundries U.S. Inc.

Inventor： Pawlak, Bartlomiej Jan ,  Rakowski, Michal ,  Bian, Yusheng

IPC: G02B6/12

Abstract: A structure comprising: a first chip comprising a first waveguide core and a first dielectric layer over the first waveguide core, the first dielectric layer having a first surface; and a second chip comprising a second waveguide core and a second dielectric layer over the second waveguide core, the second dielectric layer having a second surface adjacent to the first surface of the first dielectric layer.

公开(公告)号：EP4286904A1

公开(公告)日：2023-12-06

申请号：EP22200571.2

申请日：2022-10-10

Applicant: GlobalFoundries U.S. Inc.

Inventor： Bian, Yusheng

IPC: G02B6/12 ,  G02B6/122 ,  G02B6/30

Abstract: A structure comprising an edge coupler including a first waveguide core and a second waveguide core adjacent to the first waveguide core in a lateral direction, the first waveguide core including a first section with a first thickness and a first plurality of segments projecting in a vertical direction from the first section, and the second waveguide core including a second section with a second thickness and a second plurality of segments projecting in the vertical direction from the second section.

公开(公告)号：EP4250367A1

公开(公告)日：2023-09-27

申请号：EP22205711.9

申请日：2022-11-07

Applicant: GlobalFoundries U.S. Inc.

Inventor： PENG, Jianwei ,  YU, Hong ,  GU, Man ,  KOZARSKY, Eric S.

IPC: H01L29/66 ,  H01L29/49 ,  H01L21/28

Abstract: A structure comprising, a channel region; a gate dielectric on the channel region; source and drain structures on opposite sides of the channel region; and a gate conductor on the gate dielectric, wherein the source and drain structures include source and drain silicides, respectively, wherein the gate conductor includes a gate conductor silicide, and wherein the gate conductor silicide is thicker than the source and drain silicides.

公开(公告)号：EP4235795A1

公开(公告)日：2023-08-30

申请号：EP22199708.3

申请日：2022-10-05

Applicant: GlobalFoundries U.S. Inc.

Inventor： Malinowski, Arkadiusz ,  Derrickson, Alexander ,  Holt, Judson

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/735 ,  H01L29/161 ,  H01L29/737

Abstract: A structure for a lateral bipolar junction transistor, the structure comprising: a semiconductor substrate (10); a first terminal (16), for example a collector, including a first raised semiconductor layer (16) on the semiconductor substrate (10); a second terminal (18), for example an emitter, including a second raised semiconductor layer (18) on the semiconductor substrate (10); and an intrinsic base (12, 30, 28) on the semiconductor substrate, the intrinsic base positioned in a lateral direction between the first raised semiconductor layer (16) of the first terminal and the second raised semiconductor layer (18) of the second terminal. The intrinsic base includes a first portion (30) comprising silicon-germanium with a first germanium concentration that is graded in the lateral direction, a second region (12) with a substantially uniform low germanium concentration and a third region (28) with a substantially uniform high germanium content.

公开(公告)号：EP4213193A1

公开(公告)日：2023-07-19

申请号：EP22203386.2

申请日：2022-10-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： HOLT, Judson R. ,  JAIN, Vibhor ,  JOHNSON, Jeffrey B. ,  PEKARIK, John J.

IPC: H01L21/763 ,  H01L29/737 ,  H01L21/762 ,  H01L29/08 ,  H01L29/66 ,  H01L29/732

Abstract: A bipolar transistor structure comprising: a polycrystalline isolation layer on or over a substrate; a collector layer over the polycrystalline isolation layer, the collector layer having a first doping type, wherein a lower surface of the collector layer physically interfaces with an upper surface of the polycrystalline isolation layer; a base layer on the collector layer, the base layer having a second doping type opposite the first doping type; and an emitter layer on the base layer, the emitter layer having the first doping type, wherein the material composition of the collector layer is different from a material composition of the base layer.

公开(公告)号：EP4210091A1

公开(公告)日：2023-07-12

申请号：EP22201489.6

申请日：2022-10-14

Applicant: GlobalFoundries U.S. Inc.

Inventor： RANA, Uzma B. ,  SHANK, Steven M. ,  STAMPER, Anthony K.

IPC: H01L21/762 ,  H01L21/763 ,  H01L29/786 ,  H01L29/06

Abstract: An integrated circuit structure, comprising an active device over a bulk semiconductor substrate; and an isolation structure under the active device in the bulk semiconductor substrate, the isolation structure including a trench isolation adjacent the active device in the bulk semiconductor substrate, a dielectric layer laterally adjacent the trench isolation and over the active device, a porous semiconductor layer in the bulk semiconductor substrate under the dielectric layer laterally adjacent the trench isolation, and a polycrystalline isolation layer under the active device and the trench isolation, the porous semiconductor layer extending through the polycrystalline isolation layer.