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公开(公告)号：KR1020130109791A
公开(公告)日：2013-10-08
申请号：KR1020120031825
申请日：2012-03-28
Applicant: 삼성전자주식회사
CPC classification number: H01L24/46 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L25/18 , H01L2224/05553 , H01L2224/32145 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/49113 , H01L2224/49175 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06568 , H01L2924/10161 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2224/45664 , H01L2924/00012
Abstract: PURPOSE: A semiconductor package is inexpensively produced in large quantities and has a low loading factor. CONSTITUTION: A semiconductor package includes a master chip (120) and a slave chip (130a) laminated on a substrate (110). The master chip and the slave chip are connected in series for an external circuit. The master chip and the slave chip are connected through a bonding wire. The master chip includes a control circuit controlling the input and output of data and a signal for the slave chip. The footprint of the master chip is substantially same as the footprint of the slave chip. [Reference numerals] (110) Substrate; (120) Master chip; (130a) Slave chip
Abstract translation: 目的：半导体封装大量生产成本低，负载率低。 构成：半导体封装包括层叠在基板（110）上的主芯片（120）和从芯片（130a）。 主芯片和从芯片串联连接外部电路。 主芯片和从芯片通过接合线连接。 主芯片包括控制数据的输入和输出以及从芯片的信号的控制电路。 主芯片的占用面积与从芯片的占用面积基本相同。 （附图标记）（110）基板; （120）主芯片; （130a）从芯片
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公开(公告)号：KR1020130073714A
公开(公告)日：2013-07-03
申请号：KR1020110141709
申请日：2011-12-23
Applicant: 삼성전자주식회사
CPC classification number: H01L23/49838 , H01L23/3128 , H01L24/73 , H01L2224/16225 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2924/15311 , H01L2924/19105 , H01L2924/19106 , H01L2924/00012 , H01L2924/00
Abstract: PURPOSE: A semiconductor package is provided to facilitate a molding process by stably mounting a passive device on a substrate. CONSTITUTION: A first and a second pad (110a,110b) are separated from each other on a substrate. A part of the substrate is exposed in a region between the first and the second pad exposes. A solder resist (400) covers a part of the second pad and the first pad. The solder resist is separated from the first pad and the second pad. The length of the solder resist is same or longer as/than that of the lateral surface of the first and the second pad.
Abstract translation: 目的：提供半导体封装，以通过将无源器件稳定地安装在衬底上来促进成型工艺。 构成：第一和第二焊盘（110a，110b）在基板上彼此分离。 衬底的一部分暴露在第一和第二焊盘暴露之间的区域中。 阻焊剂（400）覆盖第二焊盘和第一焊盘的一部分。 阻焊剂与第一焊盘和第二焊盘分离。 阻焊剂的长度与第一和第二焊盘的侧表面的长度相同或更长。
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公开(公告)号：KR100876083B1
公开(公告)日：2008-12-26
申请号：KR1020070059595
申请日：2007-06-18
Applicant: 삼성전자주식회사
IPC: H01L23/48
CPC classification number: H01L2224/73104
Abstract: A semiconductor package including a semiconductor chip package is provided to improve the electric reliability of a semiconductor chip package by including a molding layer having a meniscus concave. A semiconductor chip package comprises a semiconductor chip(110), a solder ball(112) for a bump and a molding layer(120). The semiconductor chip includes a side including bonding pads, a second side facing the first side and a side. The solder ball for a bump is provided on bonding pads. The molding layer is provided so that each part of the solder balls for bump is exposed with covering the first side. The molding layer between the adjacent solder balls for bumps has a meniscus concave. The solder balls for bump comprise a cross section having a maximum diameter parallel to the first side. Height from the first side to the edge contacting with the solder ball for the bump of the meniscus concave is within 1/7 length of the maximum diameter of the solder ball to a lower part or upper part.
Abstract translation: 提供包括半导体芯片封装的半导体封装，以通过包括具有弯月面凹入的模制层来提高半导体芯片封装的电可靠性。 半导体芯片封装包括半导体芯片（110），用于凸块的焊球（112）和模制层（120）。 半导体芯片包括具有接合焊盘的一侧，面对第一侧和第二侧的第二侧。 在焊盘上提供用于凸块的焊球。 提供模制层，使得用于凸块的焊球的每个部分以覆盖第一侧的方式暴露。 用于凸块的相邻焊球之间的模制层具有弯月形凹面。 用于凸块的焊球包括具有平行于第一侧的最大直径的横截面。 从弯月形凹坑的凸块接触焊球的第一侧到边缘的高度在焊球的最大直径到下半部或上半部分的长度的1/7以内。
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公开(公告)号：KR1020080046827A
公开(公告)日：2008-05-28
申请号：KR1020060116328
申请日：2006-11-23
Applicant: 삼성전자주식회사
CPC classification number: H05K1/02 , H01L23/498 , H01L24/02 , H01L24/03 , H01L24/11 , H01L2224/03 , H01L2224/0401 , H01L2224/11009 , H01L2224/16 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H05K1/09 , H05K3/0052 , H05K3/243 , H05K3/4007 , H05K2201/0391 , H05K2201/09781 , H05K2203/0315 , H05K2203/175
Abstract: A method of fabricating an electronic device having a sacrificial anode, and an electronic device fabricated by the same are provided to suppress corrosion of a metal interconnection by forming a sacrificial pattern electrically connected to the metal interconnection, thereby preventing deterioration of electrical properties of the electrical device. A method of fabricating an electronic device comprises the steps of: preparing a substrate(1) having a first area(C) and a second area(S); forming a metal interconnection(5) extending from the first area to the second area on the substrate; forming an insulating layer(10) on the substrate; forming a sacrificial pattern(15) electrically connected to the metal interconnection, wherein the sacrificial pattern is formed on the second area to act as a sacrificial anode of cathodic projection for preventing corrosion of the metal interconnection; and patterning the insulating layer to form an opening(10b) which exposes the metal interconnection on the first area.
Abstract translation: 提供一种制造具有牺牲阳极的电子器件的方法和由其制造的电子器件，以通过形成与金属互连电连接的牺牲图案来抑制金属互连的腐蚀，从而防止电气性能的劣化 设备。 一种制造电子器件的方法包括以下步骤：制备具有第一区域（C）和第二区域（S）的衬底（1）; 形成从所述第一区域延伸到所述基板上的所述第二区域的金属互连（5）; 在所述基板上形成绝缘层（10）; 形成电连接到所述金属互连的牺牲图案（15），其中所述牺牲图案形成在所述第二区域上，以用作阴极突起的牺牲阳极，以防止金属互连的腐蚀; 以及图案化所述绝缘层以形成在所述第一区域上暴露所述金属互连的开口（10b）。
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Patent Agency Ranking
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公开(公告)号：KR101623880B1
公开(公告)日：2016-05-25
申请号：KR1020080093773
申请日：2008-09-24
Applicant: 삼성전자주식회사
CPC classification number: H01L23/49827 , H01L21/563 , H01L23/3128 , H01L23/49531 , H01L23/49575 , H01L23/49861 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L2224/32014 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/48247 , H01L2224/49175 , H01L2224/73203 , H01L2224/73207 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/06527 , H01L2225/1023 , H01L2225/1029 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/3511 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: 본발명은반도체패키지및 그제조방법에관한것으로, 적어도하나의제1 반도체칩을포함하는제1 패키지와; 외부접속단자와적어도하나의제2 반도체칩을포함하고, 상기제1 반도체패키지상에적층되는제2 패키지와; 그리고상기제1 및제2 패키지사이에배치되어상기외부접속단자와접속되므로써상기제1 및제2 패키지를전기적으로연결하는인터포저를포함하는것을특징으로한다.
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公开(公告)号：KR1020140011580A
公开(公告)日：2014-01-29
申请号：KR1020120077861
申请日：2012-07-17
Applicant: 삼성전자주식회사
CPC classification number: H01L23/49541 , H01L21/561 , H01L21/565 , H01L23/13 , H01L2224/16
Abstract: Provided is a low die apparatus for a semiconductor molding apparatus. The low die apparatus for a semiconductor molding apparatus includes a mounting surface for mounting circuit substrate chips including through holes, and window patterns extended in a first direction in the lower part of the circuit substrate chip and arranged with the through hole formed on each circuit substrate chip. The window pattern includes a first path pattern having a first width, and a second path pattern having a second width.
Abstract translation: 提供一种用于半导体成型装置的低模装置。 半导体成形装置的低模装置包括：安装电路基板芯片的安装面，其包括通孔，在电路基板芯片的下部沿第一方向延伸的窗口图案，并配置有形成在每个电路基板上的通孔 芯片。 窗口图案包括具有第一宽度的第一路径图案和具有第二宽度的第二路径图案。
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