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公开(公告)号：KR1020100043459A
公开(公告)日：2010-04-29
申请号：KR1020080102502
申请日：2008-10-20
Applicant: 삼성전자주식회사
IPC: H01L21/20
CPC classification number: H01L21/02381 , H01L21/02433 , H01L21/823462 , H01L27/10885
Abstract: PURPOSE: A semiconductor wafer and a method of manufacturing a semiconductor device using the same are provided to implement a uniform crystal face of 8F2 on an active region by controlling a notch to be parallel with the lattice structure of an active region. CONSTITUTION: A semiconductor wafer(100) includes a plane(105) formed with a monocrystal silicon and a notch(115) which is used for a reference point of a semiconductor device. The notch is arranged so that the longitudinal direction of an active region formed on the plane is parallel with the direction of a crystal lattice.
Abstract translation: 目的：提供一种半导体晶片及使用该半导体晶片的半导体器件的制造方法，通过控制与激活区域的晶格结构平行的凹口，在有源区域上实现8F2的均匀晶面。 构成：半导体晶片（100）包括由单晶硅形成的平面（105）和用于半导体器件的参考点的凹口（115）。 凹口被布置成使得形成在平面上的有源区的纵向方向与晶格的方向平行。
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公开(公告)号：KR1020090128624A
公开(公告)日：2009-12-16
申请号：KR1020080054458
申请日：2008-06-11
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L27/11519 , H01L21/265 , H01L21/28273 , H01L21/76224 , H01L21/823493 , H01L27/11521 , H01L27/2463
Abstract: PURPOSE: A memory device, a manufacturing method thereof and a semiconductor integrated circuit device including the same are provided to increase a threshold voltage by applying a relatively low voltage to a control gate. CONSTITUTION: A first conductive well(112) is formed at a first region in a semiconductor substrate. A second conductive well(114) is formed at a second region which is isolated from the first region. The first conductive well is formed by selectively ion-implanting impurities of n-type onto the first region of the semiconductor substrate. The second conductive well is formed by selectively ion-implanting impurities of p-type onto the second region of the semiconductor substrate. A device isolation film(116) is formed between the first conductive well and the second conductive well. A floating gate includes a first floating gate(132) and a second floating gate(134). The second floating gate is formed on the second conductive well between a source(104) and a drain(106).
Abstract translation: 目的：提供一种存储器件及其制造方法以及包括该存储器件的半导体集成电路器件，以通过向控制栅极施加相对较低的电压来增加阈值电压。 构成：第一导电阱（112）形成在半导体衬底中的第一区域处。 在与第一区域隔离的第二区域处形成第二导电阱（114）。 通过选择性地将n型杂质离子注入到半导体衬底的第一区域上来形成第一导电阱。 通过选择性地将p型杂质离子注入到半导体衬底的第二区上来形成第二导电阱。 在第一导电孔和第二导电孔之间形成器件隔离膜（116）。 浮置栅极包括第一浮动栅极（132）和第二浮动栅极（134）。 第二浮栅形成在源极（104）和漏极（106）之间的第二导电阱上。
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公开(公告)号：KR100827666B1
公开(公告)日：2008-05-07
申请号：KR1020070044596
申请日：2007-05-08
Applicant: 삼성전자주식회사
IPC: H01L27/092
CPC classification number: H01L27/10894 , H01L27/105 , H01L27/10897
Abstract: A semiconductor device and a manufacturing method thereof are provided to decrease thermal process stresses on cell array and periphery circuit regions by forming different insulation patterns on the respective regions. A semiconductor substrate(5) includes a cell array region and a peripheral circuit region. First and second cell gate patterns(73,74) are sequentially arranged from a center of the cell array region to the outside of the cell array region. A peripheral gate pattern(76) is arranged in the peripheral circuit region. A defining pattern is arranged between the cell array region and the peripheral circuit region and encloses the cell array region. Buried insulation patterns(108) are arranged around the first cell gate pattern, between the first and second cell gate patterns, and between the second cell gate pattern and the defining pattern. Planarized insulation patterns(168) are arranged between the defining pattern and the peripheral gate pattern and around the peripheral gate pattern.
Abstract translation: 提供半导体器件及其制造方法，通过在各个区域上形成不同的绝缘图案来降低电池阵列和外围电路区域的热处理应力。 半导体基板（5）包括单元阵列区域和外围电路区域。 第一和第二单元栅极图案（73,74）从单元阵列区域的中心依次排列到单元阵列区域的外部。 外围电路图案（76）布置在外围电路区域中。 在单元阵列区域和外围电路区域之间布置限定图案，并且包围单元阵列区域。 掩埋绝缘图案（108）围绕第一单元栅极图案，第一和第二单元栅极图案之间以及第二单元栅极图案和限定图案之间布置。 平面化绝缘图案（168）布置在限定图案和外围栅极图案之间并且围绕外围栅极图案。
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公开(公告)号：KR101853316B1
公开(公告)日：2018-04-30
申请号：KR1020120032685
申请日：2012-03-29
Applicant: 삼성전자주식회사
IPC: H01L29/78 , H01L21/336
CPC classification number: H01L29/7827 , H01L27/04 , H01L29/41766 , H01L29/4236 , H01L29/78 , H01L29/785
Abstract: 반도체소자및 이를채택하는전자장치를제공한다. 이반도체소자는반도체기판내에형성되며활성영역을한정하는필드영역을포함한다. 상기활성영역내에서로이격되도록형성된제1 소스/드레인영역및 제2 소스/드레인영역이제공된다. 상기제1 및제2 소스/드레인영역들사이의상기활성영역을가로지르며상기필드영역내로연장된게이트트렌치가제공된다. 상기게이트트렌치내의게이트구조체(gate structure)가제공된다. 상기게이트구조체는게이트전극; 상기게이트전극상에형성된절연성의게이트캐핑패턴; 상기게이트전극과상기활성영역사이의게이트유전체; 및상기게이트캐핑패턴과상기활성영역사이에개재된절연성의금속-함유물질막을포함한다.
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公开(公告)号：KR1020140091845A
公开(公告)日：2014-07-23
申请号：KR1020130003804
申请日：2013-01-14
Applicant: 삼성전자주식회사
IPC: H01L27/108 , H01L21/8242
Abstract: The present invention includes a device isolation layer which is formed in a semiconductor substrate, a buried transistor electrode, an electrode mask on the buried transistor electrode, and an active region between the device isolation layer and the electrode mask on the buried transistor electrode. The upper part of the active region has an enlarged lateral surface which is made of a conductive material such as the active region. The active region which is metallized and enlarged by depositing the same conductive material as the active region on the upper part of the active region has a wide contact area between the active region and the DC. Therefore, a DC process can be easily carried out, and a DRAM semiconductor device with good electrical properties can be obtained.
Abstract translation: 本发明包括形成在半导体衬底中的器件隔离层，埋入晶体管电极，埋入晶体管电极上的电极掩模，以及器件隔离层和掩埋晶体管电极上的电极掩模之间的有源区。 有源区域的上部具有由诸如有源区域的导电材料制成的扩大的侧表面。 通过在有源区域的上部沉积与有源区相同的导电材料进行金属化和扩大的有源区域在有源区域和DC之间具有宽的接触面积。 因此，可以容易地进行DC工艺，可以获得具有良好电性能的DRAM半导体器件。
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Patent Agency Ranking
公开(公告)号：KR1020130110599A
公开(公告)日：2013-10-10
申请号：KR1020120032685
申请日：2012-03-29
Applicant: 삼성전자주식회사
IPC: H01L29/78 , H01L21/336
CPC classification number: H01L29/7827 , H01L27/04 , H01L29/41766 , H01L29/4236 , H01L29/78 , H01L29/785 , H01L29/66621 , H01L29/66795
Abstract: PURPOSE: A transistor, a semiconductor device, and a semiconductor module including the same improve the resistance characteristics of wiring including a gate electrode of a transistor by composing the gate electrode with two or more conductive materials having different work functions. CONSTITUTION: A field region (7) limits an active region (9) by being formed within a substrate (1). A first source/drain region (60) and a second source/drain region (87) are separated from each other within the active region. A gate trench (18) includes a first part (18a) crossing the active region and a second part (18b) in the field region. A gate structure (GS) is formed within the gate trench. The gate structure includes a gate electrode (36), a gate capping pattern (45), a gate dielectric (24), and a metal-containing material film (39). The metal-containing material film is formed between the gate capping pattern and the active region.
Abstract translation: 目的：晶体管，半导体器件和包括该晶体管的半导体模块通过组合栅电极与具有不同功函的两种或多种导电材料来提高包括晶体管的栅电极的布线的电阻特性。 构成：场区域（7）通过形成在衬底（1）内而限制有源区域（9）。 第一源极/漏极区域（60）和第二源极/漏极区域（87）在有源区域内彼此分离。 栅极沟槽（18）包括与激活区域交叉的第一部分（18a）和场区域中的第二部分（18b）。 栅极结构（GS）形成在栅极沟槽内。 栅极结构包括栅极电极（36），栅极覆盖图案（45），栅极电介质（24）和含金属的材料膜（39）。 含金属材料膜形成在栅极封盖图案和有源区域之间。
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公开(公告)号：KR1020110057853A
公开(公告)日：2011-06-01
申请号：KR1020090114439
申请日：2009-11-25
Applicant: 삼성전자주식회사
IPC: H01L21/8242 , H01L27/108
CPC classification number: H01L27/10894 , H01L27/10852 , H01L27/10873 , H01L27/10876 , H01L28/91 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/6653 , H01L29/6659 , H01L29/66628
Abstract: PURPOSE: A dram semiconductor with a low density source drain using an offset single spacer and a manufacturing method thereof are provided to improve an operation voltage by forming a low density impurity after a high density impurity is formed. CONSTITUTION: An OSS(Offset Single Spacer) nitrification layer(144) is formed on a first oxide layer(142). A second oxide layer spacer is formed on the OSS nitrification layer. A high density source and drain layer is formed on a semiconductor substrate(100). A nitrification layer spacer is formed by anisotropically etching the OSS nitrification layer. A low density impurity layer is formed by using the nitrification layer spacer. An interlayer insulation layer(160) with a capacitor electrode structure is formed on the semiconductor substrate and the gate electrode.
Abstract translation: 目的：提供使用偏移单间隔物的具有低密度源极漏极的串联半导体及其制造方法，以在形成高密度杂质之后形成低密度杂质来提高工作电压。 构成：在第一氧化物层（142）上形成OSS（Offset Single Spacer）硝化层（144）。 在OSS硝化层上形成第二氧化物层隔离物。 在半导体衬底（100）上形成高密度源极和漏极层。 通过各向异性蚀刻OSS硝化层形成硝化层间隔物。 通过使用硝化层间隔物形成低密度杂质层。 在半导体衬底和栅电极上形成具有电容器电极结构的层间绝缘层（160）。
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公开(公告)号：KR101809463B1
公开(公告)日：2017-12-15
申请号：KR1020110041295
申请日：2011-05-02
Applicant: 삼성전자주식회사
IPC: H01L29/78 , H01L21/762 , H01L21/336
CPC classification number: H01L29/4236 , H01L21/2652 , H01L21/2658 , H01L21/76224 , H01L29/66621
Abstract: 반도체소자및 반도체소자의제조방법에있어서, 기판에액티브영역을정의하기위한제1 트렌치내벽상에, 하부및 상부에각각제1 도전형의제1 불순물및 제2 도전형의제2 불순물이도핑된폴리실리콘막패턴과, 제1 트렌치의나머지부분에절연구조물을형성하여소자분리막구조물을형성한다. 폴리실리콘막패턴의하부에인접한액티브영역에제2 도전형의제3 불순물을주입하여웰 영역을형성한다. 게이트구조물을형성한후, 폴리실리콘막패턴의상부에인접한액티브영역에제1 도전형의제4 불순물을주입하여소스/드레인을형성한다. 상하부에서로다른도전형의불순물이도핑된폴리실리콘막패턴에의해, 각웰 영역및 소스/드레인의인접영역에서캐리어상쇄효과가발생될수 있다.
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公开(公告)号：KR101781482B1
公开(公告)日：2017-09-26
申请号：KR1020100130942
申请日：2010-12-20
Applicant: 삼성전자주식회사
IPC: H01L27/112 , H01L23/525
CPC classification number: H01L23/5252 , H01L27/11206 , H01L2924/0002 , H01L2924/00
Abstract: 본발명개념은안티퓨즈소자, 이를포함하는반도체장치및 시스템에관한것으로서, 더욱구체적으로는, 채널영역에브레이크다운방지물질막을포함하는안티퓨즈소자, 이를포함하는반도체장치및 시스템에관한것이다. 본발명개념의안티퓨즈소자및 반도체장치를이용하면별도의추가공정없이도칩 크기감소가가능하여원가절감에기여할수 있고전류산포가개선되는효과를얻을수 있다.
Abstract translation: 本发明构思涉及一种半导体器件，并且包括一个系统涉及一种半导体器件和包括该反熔丝元件的系统中，从而，所述反熔丝元件包括更具体地，防击穿到沟道区材料膜，它。 通过使用本发明的反熔丝元件和半导体器件，可以在没有任何附加工艺的情况下减小芯片尺寸，从而有助于降低成本并改善电流扩展。
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公开(公告)号：KR101721115B1
公开(公告)日：2017-03-30
申请号：KR1020100003131
申请日：2010-01-13
Applicant: 삼성전자주식회사
CPC classification number: G11C8/14
Abstract: 서브워드라인드라이버를포함하는반도체소자에관해개시한다. 상기반도체소자는, 메모리셀에동작신호를전달하는제 1 서브워드라인및 제 2 서브워드라인, 제 1 서브워드라인및 제 2 서브워드라인에동작신호를선택적으로전달하는메인워드라인, 및제 1 서브워드라인및 제 2 서브워드라인사이에연결된스위칭트랜지스터를포함하고, 스위칭트랜지스터의게이트는메인워드라인과연결된다.
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