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公开(公告)号：KR100532434B1
公开(公告)日：2005-11-30
申请号：KR1020030029368
申请日：2003-05-09
Applicant: 삼성전자주식회사
IPC: H01L27/108
CPC classification number: H01L27/10852 , C23C16/405 , C23C16/56 , H01L21/02181 , H01L21/0228 , H01L21/0234 , H01L21/02356 , H01L21/31645 , H01L27/10817 , H01L27/10855 , H01L28/91 , Y10S438/957
Abstract: HfO
2 유전막을 채용하는 고집적 반도체 메모리 소자의 커패시터 제조 방법에 관하여 개시한다. 본 발명에서는 HfO
2 막을 형성한 후 저온에서 플라즈마 처리하여 HfO
2 막을 결정화시킴으로써 안정적인 누설 전류 특성을 얻는다. 본 발명에서는 하부 전극 위에 형성된 비정질 HfO
2 막을 250 ∼ 450℃의 온도에서 질소 함유 가스의 플라즈마 분위기에 노출시켜 결정화된 HfO
2 유전막을 형성한다. 결정화된 HfO
2 막 위에 상부 전극을 형성한다. 저온에서 HfO
2 막을 결정화시키므로 하부 구조물에 고온 공정에 따른 악영향을 미치지 않고 누설 전류 특성을 향상시킬 수 있다.-
公开(公告)号：KR1020050011151A
公开(公告)日：2005-01-29
申请号：KR1020030050125
申请日：2003-07-22
Applicant: 삼성전자주식회사
IPC: H01L27/108
CPC classification number: H01L28/91 , H01L21/76877 , H01L27/10855 , H01L27/11507 , H01L28/75
Abstract: PURPOSE: A method of forming a semiconductor device with a capacitor composed of electrodes containing metal is provided to reduce contact resistance between a lower electrode and a conductive plug by using a metal silicide layer. CONSTITUTION: A conductive plug(108) is connected with a predetermined region of a semiconductor substrate(100) through a lower interlayer dielectric(106). A mold layer(114) is formed on the entire surface of the resultant structure. An opening(116) for exposing the conductive plug to the outside is formed by patterning selectively the mold layer. A metal silicide layer(120) is formed on the exposed conductive plug. A lower electrode is formed along an inner surface of the opening.
Abstract translation: 目的：提供一种形成具有由含有金属的电极组成的电容器的半导体器件的方法，以通过使用金属硅化物层来降低下电极和导电插塞之间的接触电阻。 构成：导电插头（108）通过下层间电介质（106）与半导体衬底（100）的预定区域连接。 在所得结构的整个表面上形成模具层（114）。 用于将导电插塞暴露于外部的开口（116）通过选择性地构图模具层而形成。 在暴露的导电插塞上形成金属硅化物层（120）。 沿着开口的内表面形成下电极。
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公开(公告)号：KR100464855B1
公开(公告)日：2005-01-06
申请号：KR1020020044318
申请日：2002-07-26
Applicant: 삼성전자주식회사
IPC: H01L21/205
CPC classification number: H01L21/0228 , C23C16/405 , C23C16/45531 , C23C16/45542 , C23C16/45553 , H01L21/02194 , H01L21/02205 , H01L21/02274 , H01L21/02277 , H01L21/02337 , H01L21/02348 , H01L21/31604 , H01L21/31683 , H01L28/90
Abstract: A thin film is formed using an atomic layer deposition process, by introducing a first reacting material including tantalum precursors and titanium precursors onto a substrate. A portion of the first reacting material is chemisorbed onto the substrate. Then, a second reacting material including oxygen is introduced onto the substrate. A portion of the second reacting material is also chemisorbed onto the substrate, to form an atomic layer of a solid material on the substrate. The solid material may be used as a dielectric layer of the capacitor and/or a gate dielectric layer of the transistor.
Abstract translation: 使用原子层沉积工艺，通过将包含钽前体和钛前体的第一反应材料引入到衬底上来形成薄膜。 第一反应材料的一部分被化学吸附到基底上。 然后，将包含氧的第二反应材料引入到基板上。 一部分第二反应材料也被化学吸附到基底上，以在基底上形成固体材料的原子层。 固体材料可以用作电容器的介电层和/或晶体管的栅极介电层。
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公开(公告)号：KR1020040093618A
公开(公告)日：2004-11-06
申请号：KR1020030027556
申请日：2003-04-30
Applicant: 삼성전자주식회사
IPC: H01L27/10
CPC classification number: H01L27/10855 , H01L21/76889 , H01L21/76895 , H01L27/10817 , H01L27/10894 , H01L27/10897
Abstract: PURPOSE: A semiconductor device and a forming method thereof are provided to restrain leakage current and to improve the reliability of the device by forming the second pad contact plug between a resistor and a metal contact plug. CONSTITUTION: A semiconductor substrate(100) includes a cell array region(A) and a peripheral region(B). A lower interlayer dielectric(102) is formed on the substrate. A buried contact plug(106a) is electrically connected with the substrate through the lower interlayer dielectric within the cell array region. A resistor(108) is formed on the lower interlayer dielectric within the peripheral region. The first interlayer dielectric(112) is formed thereon. The first pad contact plug(118a) is electrically connected with the buried contact plug through the first interlayer dielectric. The second pad contact plug(118b) is electrically connected with the resistor through the first interlayer dielectric. An ohmic layer(115) is formed between the first pad contact plug and the buried contact plug and between the second pad contact plug and the resistor. A capacitor is electrically connected with the first pad contact plug. The second interlayer dielectric(134) is formed thereon. A metal contact plug(140) is electrically connected with the second contact plug through the first and second interlayer dielectric.
Abstract translation: 目的：提供半导体器件及其形成方法以通过在电阻器和金属接触插塞之间形成第二焊盘接触插塞来抑制漏电流并提高器件的可靠性。 构成：半导体衬底（100）包括电池阵列区域（A）和外围区域（B）。 在该基板上形成下部层间电介质（102）。 埋入式接触插头（106a）通过电池阵列区域内的下层间电介质与衬底电连接。 在外围区域中的下层间电介质上形成电阻（108）。 第一层间电介质（112）形成在其上。 第一焊盘接触插头（118a）通过第一层间电介质与埋入接触插塞电连接。 第二焊盘接触插头（118b）通过第一层间电介质与电阻器电连接。 在第一焊盘接触插头和埋入接触插头之间以及第二焊盘接触插头和电阻器之间形成欧姆层（115）。 电容器与第一焊盘接触插头电连接。 在其上形成第二层间电介质（134）。 金属接触插塞（140）通过第一和第二层间电介质与第二接触插塞电连接。
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公开(公告)号：KR100421034B1
公开(公告)日：2004-03-04
申请号：KR1019990050903
申请日：1999-11-16
Applicant: 삼성전자주식회사
IPC: H01L21/027
CPC classification number: G03F7/40
Abstract: A method for forming a fine pattern in a semiconductor substrate, by coating a target layer to be etched on a semiconductor substrate with a resist composition including at least one compound capable of forming a photoresist pattern by a photolithography process, and a free radical initiator. The free radical initiator is capable of being decomposed by a thermal process at a temperature equal to or higher than the glass transition temperature of the at least one compound. A lithography process is performed on the resist compound layer to form a photoresist pattern. The resist compound layer having the photoresist pattern formed therein is heated to a temperature equal to or higher than the glass transition temperature of the at least one compound, and wherein a partial cross-linking reaction in the resist composition occurs.
Abstract translation: 一种在半导体衬底中形成精细图案的方法，该方法通过用包含至少一种能够通过光刻工艺形成光致抗蚀剂图案的化合物的抗蚀剂组合物在半导体衬底上涂覆待蚀刻层以及自由基引发剂来形成。 自由基引发剂能够在等于或高于至少一种化合物的玻璃化转变温度的温度下通过热过程分解。 在抗蚀剂化合物层上执行光刻工艺以形成光刻胶图案。 将其中形成有光致抗蚀剂图案的抗蚀剂化合物层加热至等于或高于所述至少一种化合物的玻璃化转变温度的温度，并且其中发生抗蚀剂组合物中的部分交联反应。
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Patent Agency Ranking
公开(公告)号：KR1020040009935A
公开(公告)日：2004-01-31
申请号：KR1020020044318
申请日：2002-07-26
Applicant: 삼성전자주식회사
IPC: H01L21/205
CPC classification number: H01L21/0228 , C23C16/405 , C23C16/45531 , C23C16/45542 , C23C16/45553 , H01L21/02194 , H01L21/02205 , H01L21/02274 , H01L21/02277 , H01L21/02337 , H01L21/02348 , H01L21/31604 , H01L21/31683 , H01L28/90
Abstract: PURPOSE: A method for forming a thin film and a method for forming a capacitor and a transistor using the same are provided to improve a dielectric constant and reduce the amount of leakage current by using an atomic layer deposition method. CONSTITUTION: The first reaction material(2) including a tantalum precursor and a titanium precursor is introduced to a substrate(1). The first reaction material(2) is partially absorbed on the upper surface of the substrate(1) by introducing the first reaction material to the substrate. The second reaction material(6) including oxygen is introduced to the substrate. A solid material(8) is formed on the upper surface by absorbing partially the second reaction material(6) on the upper surface of the substrate. The tantalum precursor is formed with one material selected from a group including TaCl5, Ta(OC2H5)5, Ta(OC4H9)5, Ta(OC2H5)(OC3H7)4, and TAT-DMAE. The titanium precursor is formed with one material selected form a group including TiCl4, Ti(OCH3)4, Ti(OC2H5)4, Ti(OC3H7)4, Ti(OC4H9)4, Ti(OC2H5)(OC3H7)4, Ti(OC3H7)2(O2C11H19)2, and Ti(OEt)2(DMAE)2.
Abstract translation: 目的：提供一种形成薄膜的方法以及使用其形成电容器和晶体管的方法，以通过使用原子层沉积方法来提高介电常数并减少漏电流量。 构成：将包含钽前体和钛前体的第一反应材料（2）引入基材（1）。 第一反应材料（2）通过将第一反应材料引入基底而被部分地吸收在基底（1）的上表面上。 将包含氧的第二反应材料（6）引入基材。 通过在基板的上表面部分地吸收第二反应材料（6），在上表面上形成固体材料（8）。 钽前体由选自TaCl 5，Ta（OC 2 H 5）5，Ta（OC 4 H 9）5，Ta（OC 2 H 5）（OC 3 H 7）4和TAT-DMAE）的一种材料形成。 钛前体由选自TiCl4，Ti（OCH3）4，Ti（OC2H5）4，Ti（OC3H7）4，Ti（OC4H9）4，Ti（OC2H5）（OC3H7）4，Ti（ OC 3 H 7）2（O 2 C 11 H 19）2和Ti（OEt）2（DMAE）2。
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公开(公告)号：KR1020090051634A
公开(公告)日：2009-05-22
申请号：KR1020070118115
申请日：2007-11-19
Applicant: 삼성전자주식회사
IPC: H01L21/8242 , H01L27/108
CPC classification number: H01G4/33 , H01G4/1218 , H01G4/20 , H01L28/56 , H01L28/91
Abstract: 향상된 전기적 특성을 갖는 캐패시터 및 그 제조 방법이 개시된다. 캐패시터는 콘택 영역을 갖는 기판 상에 형성된 하부 전극, 하부 전극 상에 형성된 유전체 구조물 및 유전체 구조물 상에 형성된 상부 전극을 포함한다. 유전체 구조물은 적어도 2개의 유전막 패턴들과 유전막 패턴들 사이에 개재되는 적어도 하나의 버퍼 유전막 패턴을 포함한다. 2 이상의 유전막 패턴들 사이에 개재된 버퍼 유전막 패턴을 구비하는 유전체 구조물을 통해 캐패시터의 유전율을 개선하면서 누설 전류를 감소시킬 수 있다.
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公开(公告)号：KR1020080048774A
公开(公告)日：2008-06-03
申请号：KR1020060119161
申请日：2006-11-29
Applicant: 삼성전자주식회사
IPC: H01L27/108 , H01L27/04
CPC classification number: H01L28/91 , H01L27/10855
Abstract: A method for forming a capacitor bottom electrode is provided to maintain a profile of the capacitor bottom electrode and to increase a height of a mold oxide without improving a dry-etch process. A first etch-stop layer and a first mold oxide layer(220) are sequentially formed on a semiconductor substrate including a conductive pad and an interlayer dielectric. A first opening for exposing the conductive pad is formed by etching partially the etch-stop layer and the first mold oxide layer. A sacrificial layer pattern is formed to bury the first opening. A second etch-stop layer and a second mold oxide layer are sequentially formed on the sacrificial layer pattern and the first mold oxide. A second opening for exposing an upper surface of the sacrificial layer pattern is formed by etching partially the second etch-stop layer and the second mold oxide layer. A third opening is formed by etching the sacrificial layer pattern. A lower electrode pattern is formed on an inner surface of the third opening.
Abstract translation: 提供形成电容器底部电极的方法以保持电容器底部电极的轮廓并且在不改进干蚀刻工艺的情况下增加模制氧化物的高度。 在包括导电焊盘和层间电介质的半导体衬底上依次形成第一蚀刻停止层和第一模制氧化物层（220）。 用于暴露导电焊盘的第一开口通过部分地蚀刻蚀刻停止层和第一模具氧化物层而形成。 形成牺牲层图案以埋设第一开口。 第二蚀刻停止层和第二模具氧化物层依次形成在牺牲层图案和第一模制氧化物上。 用于暴露牺牲层图案的上表面的第二开口通过部分蚀刻第二蚀刻停止层和第二模具氧化物层而形成。 通过蚀刻牺牲层图案形成第三开口。 在第三开口的内表面上形成下电极图案。
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公开(公告)号：KR100712525B1
公开(公告)日：2007-04-30
申请号：KR1020050074915
申请日：2005-08-16
Applicant: 삼성전자주식회사
IPC: H01L21/8242
CPC classification number: H01G4/10 , H01G4/33 , Y10T29/435
Abstract: 본 발명은 커패시터 및 그 제조방법에 관한 것이다. 본 발명에 따른 커패시터는, 하부전극 상에 전처리막을 구비하므로 유전막과의 반응이 억제되어 커패시터 특성 열화를 방지할 수 있다. 그리고, 유전막은 적어도 일부가 질화 또는 산화된 것이므로, 누설전류 증가를 억제할 수 있어 고집적 디램에 적용할 수 있다. 본 발명에 따른 커패시터 제조방법에서는 배치 타입(batch type) 장비 안에서 유전막 형성 전/후의 플라즈마 처리를 유전막 형성 단계와 연속적으로 진행하므로, 플라즈마 처리와 유전막 증착 사이의 정체 시간이 웨이퍼별로 달라질 우려가 전혀 없다. 따라서, 웨이퍼간의 막질 특성에서 변동이 적은 커패시터를 제조할 수 있다. 그리고, 배치 타입 장비를 이용하므로 생산성이 현저히 향상되는 효과가 있다.
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公开(公告)号：KR1020070014475A
公开(公告)日：2007-02-01
申请号：KR1020050069139
申请日：2005-07-28
Applicant: 삼성전자주식회사
IPC: H01L21/8242
CPC classification number: H01L21/02181 , H01L21/02178 , H01L21/022 , H01L21/0228 , H01L21/3142 , H01L21/3162 , H01L21/31645 , H01L28/91
Abstract: A method for fabricating an MIM capacitor is provided to increase the surface area of an electrode by making photoresist cover a conductive layer for forming a cylindrical lower electrode. An interlayer dielectric having a contact plug is formed on a semiconductor substrate. An etch stop layer is formed on the interlayer dielectric. A mold layer is formed on the etch stop layer, including an opening exposing the contact plug. A first conductive layer for a lower electrode is formed on the lateral and the lower surfaces of the opening. A photoresist layer is formed on the first conductive layer. The lower electrode is formed which is node-separated from the first conductive layer. The mold layer and the photoresist layer are eliminated. A complex dielectric layer is formed on the lower electrode. A second conductive layer is formed on the complex dielectric layer to complete an upper electrode. The complex dielectric layer is composed of an HfO2 dielectric layer having a thickness greater than 20 angstroms and smaller than 50 angstroms and an Al2O3 dielectric layer formed on the HfO2 dielectric layer. The Al2O3 dielectric layer has a thickness formed by subtracting the thickness of the HfO2 dielectric layer from the real thickness of an equivalent dielectric oxide layer that is set to make the Al2O3 dielectric layer have predetermined capacitance. The Al2O3 dielectric layer can have a thickness of at least 15 angstroms.
Abstract translation: 提供一种用于制造MIM电容器的方法，通过使光致抗蚀剂覆盖用于形成圆柱形下电极的导电层来增加电极的表面积。 在半导体衬底上形成具有接触插塞的层间电介质。 在层间电介质上形成蚀刻停止层。 在蚀刻停止层上形成模具层，包括暴露接触插塞的开口。 用于下电极的第一导电层形成在开口的侧表面和下表面上。 在第一导电层上形成光致抗蚀剂层。 形成与第一导电层节点分离的下电极。 去除模层和光致抗蚀剂层。 复合电介质层形成在下电极上。 在复合电介质层上形成第二导电层以完成上电极。 复合介电层由厚度大于20埃且小于50埃的HfO 2电介质层和形成在HfO 2电介质层上的Al2O3电介质层组成。 Al 2 O 3电介质层具有通过从设定为使Al 2 O 3电介质层具有预定电容的等效电介质氧化物层的实际厚度减去HfO 2电介质层的厚度而形成的厚度。 Al 2 O 3介电层可以具有至少15埃的厚度。
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