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公开(公告)号：KR1020060089261A
公开(公告)日：2006-08-09
申请号：KR1020050009845
申请日：2005-02-03
Applicant: 재단법인서울대학교산학협력재단 , 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L29/66833 , H01L21/265 , H01L21/28282 , H01L21/823892 , H01L29/792
Abstract: 본 발명은 다층의 도핑층을 갖는 소노스(SONOS) 메모리 셀을 이용한 낸드(NAND) 플래시 메모리 어레이 및 그 동작방법에 관한 것이다.
종래 소노스 메모리 셀의 구조와 달리 본 발명에서 사용되는 메모리 셀은 액티브 영역에 다층의 도핑층을 적절히 형성함으로써, 소스/드레인 영역과 PN 접합을 이루는 부분에서 전자가 밴드간 터널링이 되도록 유도하고, 상기 전자를 소정의 역 바이어스 상태에서 가속시켜 애벌런치 현상을 유도하여 이 때 생성된 홀을 각 소노스 메모리 셀의 다중 유전층으로 주입시키는 방식으로 프로그램하고, 이레이즈시에는 FN 터널링으로 채널에 있는 전자를 상기 각 셀의 다중 유전층으로 주입시키는 방식으로 낸드 플래시 메모리 어레이를 동작하는 방법을 제공한다.
SONOS, 플래시 메모리, 터널링, 애벌런치, NAND-
公开(公告)号：KR1020060089260A
公开(公告)日：2006-08-09
申请号：KR1020050009844
申请日：2005-02-03
Applicant: 재단법인서울대학교산학협력재단 , 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L21/823892 , H01L21/041 , H01L21/2652
Abstract: 본 발명은 액티브 영역에 다층의 도핑층을 갖는 소노스(SONOS) 형태의 플래시 메모리 셀의 구조 및 그 제조방법과 동작방법에 관한 것이다.
종래 소노스 메모리 셀의 구조와 달리 본 발명은 액티브 영역에 다층의 도핑층을 적절히 형성함으로써, 소스/드레인 영역과 PN 접합을 이루는 부분에서 전자가 밴드간 터널링이 되도록 유도하고, 상기 전자를 소정의 역 바이어스 상태에서 가속시켜 애벌런치 현상을 유도하여 이 때 생성된 홀을 소노스 메모리 셀의 다중 유전층으로 주입시키는 방식으로 프로그램하고, 이레이즈시에는 FN 터널링으로 채널에 있는 전자를 상기 다중 유전층으로 주입시키는 방식으로 셀을 동작하는 방법을 제공한다.
SONOS, 플래시 메모리, 터널링, 애벌런치-
公开(公告)号：KR100538542B1
公开(公告)日：2005-12-22
申请号：KR1020030004002
申请日：2003-01-21
Applicant: 재단법인서울대학교산학협력재단 , 이진호
IPC: H01L29/786
Abstract: 본 발명은 유기 박막 트랜지스터 및 그의 제조방법에 관한 것으로, 기존의 유기 박막 트랜지스터를 제조 공정 중에, 소스와 드레인 전극을 표면 처리하는 물질과 게이트 절연막을 표면 처리하는 OTS(octadecyl trichlorosilane)를 동시에 사용할 경우에 소자의 특성이 저하되는 문제점과 각기 분리하여 표면 처리할 경우 복잡한 공정이 수행되는 문제점을 본 발명에서는 모노클로러벤젠(monochlorobenzen)에 의해 희석시킨 PMMA(poly-(methyl methacrylate))용액을 소스와 드레인 전극 및 게이트 절연막에 한 번의 스핀 코팅한 후, 유기 반도체 물질을 증착시킴으로써 해결한다.
따라서, 본 발명은 소스 및 드레인 전극과 게이트 절연막에 그레인 사이즈가 크고, 잘 성장되는 유기 반도체 물질막을 형성할 수 있게 되어서, 소자의 캐리어 이동도를 향상시킬 수 있고 제조 공정 시간을 단축시킬 수 있는 효과가 있다.-
公开(公告)号：KR1020040104051A
公开(公告)日：2004-12-10
申请号：KR1020030035440
申请日：2003-06-02
Applicant: 재단법인서울대학교산학협력재단
IPC: G09G3/30
Abstract: PURPOSE: A method for driving the column of a pixel array of a micro display and a driving circuit for the same are provided to drastically reduce the occupied area by removing the latches in the column of a conventional column driving circuit. CONSTITUTION: An apparatus for driving the column of a pixel array of a micro display includes a shift register, a digital-to-analog converter(DAC), a DAC operation control circuit and a column driving switch. The shift register generates a digital signal to select each column of pixel array. The DAC converts the digital input signal to an analog signal to drive each column of pixel array in response to the output signal of the shift register. The DAC operation control circuit connects its input terminals to the first output terminal of a specific block and the first output terminal of the neighboring block to operate the DAC at the signal corresponding to the specific block. And, the column driving switch is connected to the output terminals of the shift register and the output terminals of the DAC to control the driving of each column of the pixel array.
Abstract translation: 目的：提供一种用于驱动微显示器的像素阵列的列和用于其的驱动电路的方法，以通过去除常规列驱动电路的列中的锁存器来大大减小占用面积。 构成：用于驱动微型显示器的像素阵列的列的装置包括移位寄存器，数 - 模转换器（DAC），DAC操作控制电路和列驱动开关。 移位寄存器产生数字信号以选择每列像素阵列。 DAC将数字输入信号转换为模拟信号，以响应于移位寄存器的输出信号驱动像素阵列的每一列。 DAC操作控制电路将其输入端连接到特定块的第一输出端和相邻块的第一输出端，以对应于特定块的信号操作DAC。 并且，列驱动开关连接到移位寄存器的输出端和DAC的输出端，以控制像素阵列的每列的驱动。
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公开(公告)号：KR100444270B1
公开(公告)日：2004-08-12
申请号：KR1020020039146
申请日：2002-07-06
Applicant: 재단법인서울대학교산학협력재단
IPC: H01L21/8244
CPC classification number: B82Y10/00 , H01L27/11 , H01L29/66439 , H01L29/66772 , H01L29/7613 , H01L29/78654 , Y10S438/962
Abstract: The present invention relates to a method for fabricating semiconductor device with negative differential conductance or transconductance. According to the present invention, a fabrication process thereof can be simplified by using an SOI (Silicon-On-Insulator) substrate, and a tunneling device exhibiting the negative differential conductance or transconductance at room temperature can be implemented by using P+-N+ junction barriers as tunneling barriers and implanting impurity ions into a channel region so that their density is higher than the effective density of states where electrons or holes can exist thereon. Since the semiconductor device with the negative differential conductance or transconductance can be also be implemented even at room temperature, there is an advantage in that the present invention can be applied to an SRAM or a logic device using a device which can be turned on/off in response to a specific voltage.Further, according to the fabrication method of the present invention. miniaturization of the device can be easily made, and the reproducibility and the mass productivity of the process can be enhanced. Simultaneously, the gate, the source/drain and the channel regions are formed by the self-aligned process. Thus, there is another advantage in that a gate pitch can also be reduced.In addition, there is a further advantage in that the semiconductor device fabricated according to the present invention has the characteristic of a single electron transistor by using the channel region as the quantum dot and the two P+-N+ junctions as the tunneling barriers.
Abstract translation: 本发明涉及一种制造具有负微分电导或跨导的半导体器件的方法。 根据本发明，通过使用SOI（绝缘体上硅）衬底可以简化其制造工艺，并且可以通过使用P + -N +结势垒实现在室温下呈现负微分电导或跨导的隧穿器件 作为隧道势垒并将杂质离子注入到沟道区中，使得它们的密度高于其上可存在电子或空穴的状态的有效密度。 由于即使在室温下也可以实现具有负的微分电导或跨导的半导体器件，因此具有的优点是本发明可以应用于使用可以开/关的器件的SRAM或逻辑器件 以响应特定的电压。此外，根据本发明的制造方法。 可以容易地实现装置的小型化，并且可以提高该过程的再现性和批量生产率。 同时，通过自对准过程形成栅极，源极/漏极和沟道区域。 因此，还有一个优点是栅极节距也可以减小。此外，还有一个优点是根据本发明制造的半导体器件具有单个电子晶体管的特性，其中通过使用沟道区作为 量子点和两个P + -N +结作为隧道势垒。
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Patent Agency Ranking
公开(公告)号：KR1020030089162A
公开(公告)日：2003-11-21
申请号：KR1020020027239
申请日：2002-05-17
Applicant: 재단법인서울대학교산학협력재단
IPC: H01L29/78
Abstract: PURPOSE: A method for manufacturing an FET(Field Effect Transistor) having an LDD(Lightly Doped Drain) is provided to be capable of improving the reproductivity of a process, automating the process, and preventing contamination. CONSTITUTION: After forming the first oxide layer at the upper portion of an isolating layer, the first oxide sidewalls(45a,45b) are formed at both sides of a gate(43a) by carrying out the first dry etching process at the first oxide layer. After forming a nitride layer at the upper portion of the resultant structure, nitride sidewalls are formed at each outer portion of the first oxide sidewalls by carrying out the second dry etching process at the nitride layer. Then, a source and drain region(48a,48b) are formed at a semiconductor substrate(41) by implanting ions. The nitride sidewalls are removed by carrying out the third dry etching process for remaining the first oxide sidewalls alone. At this time, the insulating layer is selectively etched.
Abstract translation: 目的：提供具有LDD（轻掺杂漏极）的FET（场效应晶体管）的制造方法，能够提高工艺的再现性，使工艺自动化，防止污染。 构成：在隔离层的上部形成第一氧化物层之后，通过在第一氧化物层进行第一干蚀刻工艺，在栅极（43a）的两侧形成第一氧化物侧壁（45a，45b） 。 在所得结构的上部形成氮化物层之后，通过在氮化物层进行第二次干蚀刻工艺，在第一氧化物侧壁的每个外部形成氮化物侧壁。 然后，通过注入离子在半导体衬底（41）处形成源区和漏区（48a，48b）。 通过执行用于仅剩下第一氧化物侧壁的第三干蚀刻工艺来去除氮化物侧壁。 此时，绝缘层被选择性蚀刻。
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公开(公告)号：KR1020030088309A
公开(公告)日：2003-11-19
申请号：KR1020020026415
申请日：2002-05-14
Applicant: 재단법인서울대학교산학협력재단
IPC: H01L29/78
Abstract: PURPOSE: A FET(Field Effect Transistor) and a method for manufacturing the same are provided to be capable of easily forming an ultra-small channel, reducing the delay and resistance of a gate for improving the operation of the FET, and operating a source/drain with low resistance. CONSTITUTION: A FET is provided with an SOI(Silicon On Insulator) substrate(10), a source and drain region(3a,3b) spaced apart from each other at the silicon layer of the SOI substrate, and a pair of first insulating sidewalls(14a,14b) formed at the upper portion of the silicon layer between the source/drain region. The FET further includes a gate electrode(16'') formed at the predetermined upper portion of the silicon layer, a gate isolating layer(15) located between the gate electrode and the resultant structure, the second sidewalls(17a,17b) formed at both sides of the gate electrode, and silicide layers(18,19,20) selectively formed at the upper portion of the resultant structure.
Abstract translation: 目的：提供FET（场效应晶体管）及其制造方法，以便能够容易地形成超小通道，减小栅极的延迟和电阻，以改善FET的工作，并且操作源极 /漏低电阻。 构成：FET设置有SOI（绝缘体上硅）衬底（10），在SOI衬底的硅层处彼此间隔开的源极和漏极区域（3a，3b）以及一对第一绝缘侧壁 （14a，14b），形成在源极/漏极区之间的硅层的上部。 FET还包括形成在硅层的预定上部的栅电极（16“），位于栅极和所得结构之间的栅极隔离层（15），形成在第二侧壁 栅电极的两侧，以及选择性地形成在所得结构的上部的硅化物层（18,19,20）。
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28.发明公开핀분리층이 내재된 수직 채널의 노아 플래시 메모리 어레이 有权NOR FLASH MEMORY ARRAY WITH VERTICAL CHANNEL BUILTIN FIN-SPLIT LAYER
公开(公告)号：KR1020100003923A
公开(公告)日：2010-01-12
申请号：KR1020080063980
申请日：2008-07-02
Applicant: 재단법인서울대학교산학협력재단
IPC: H01L27/115 , H01L29/78
CPC classification number: H01L27/2463 , H01L21/28273 , H01L21/28282 , H01L29/513
Abstract: PURPOSE: A NOR flash memory array of a vertical channel embedding a fin separation layer is provided to prevent a leakage current between bit lines by arranging the pin separation layer between the silicon fins. CONSTITUTION: A NOR flash memory array includes a silicon substrate(10), a charge storage(60), and a gate line(70). The silicon substrate has the silicon fins(12a,12b). The charge storage is arranged on the silicon fins. The gate lines are positioned on the charge storage and cross the silicon fins. The NOR flash memory array includes a fin separation layer(11). The fin separation layer is arranged between the silicon fins.
Abstract translation: 目的：提供嵌入散热片分离层的垂直通道的NOR闪存阵列，以通过在硅散热片之间布置针分离层来防止位线之间的漏电流。 构成：NOR闪存阵列包括硅衬底（10），电荷存储器（60）和栅极线（70）。 硅衬底具有硅散热片（12a，12b）。 电荷存储器设置在硅散热片上。 栅极线位于电荷存储器上并且穿过硅散热片。 NOR闪存阵列包括鳍分离层（11）。 翅片分离层布置在硅散热片之间。
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公开(公告)号：KR1020090118299A
公开(公告)日：2009-11-18
申请号：KR1020080044005
申请日：2008-05-13
Applicant: 재단법인서울대학교산학협력재단
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L27/2463 , H01L21/28273 , H01L27/11521 , H01L27/11551 , H01L27/2436
Abstract: PURPOSE: An AND type flash memory array of a vertical laminate structure, a manufacturing method thereof, and an operating method are provided to perform high integration by forming a local bit line and a local source line in a silicon pin of each layer. CONSTITUTION: An AND type flash memory array of a vertical laminate structure includes one or more bit lines, a local bit line, a memory cell, a local source line, a common source line, a drain selecting line, a source selecting line, and word lines. The local bit line is connected to each bit line(98a,98b,98c) by a first selecting transistor. A plurality of memory cells are parallel connected by using the local bit line as a common drain line. The local source line is commonly connected to a source of each memory cell. The common source line is vertically arranged with each bit line in which the local source line is connected by a second selecting transistor. The drain selecting line and the source selecting line are connected to a gate of the first selecting transistor and a gate of the second selecting transistor. The word lines are connected to a gate of each memory cell.
Abstract translation: 目的：提供垂直层压结构的AND型闪速存储器阵列，其制造方法和操作方法，以通过在每层的硅引脚中形成局部位线和局部源极线来执行高集成度。 构成：垂直层叠结构的AND型闪速存储阵列包括一个或多个位线，局部位线，存储单元，局部源极线，公共源极线，漏极选择线，源选择线和 字线。 局部位线由第一选择晶体管连接到每个位线（98a，98b，98c）。 多个存储单元通过使用本地位线作为公共漏极线并联连接。 本地源线通常连接到每个存储单元的源。 公共源极线垂直地布置有每个位线，其中本地源极线通过第二选择晶体管连接。 漏极选择线和源选择线连接到第一选择晶体管的栅极和第二选择晶体管的栅极。 字线连接到每个存储单元的门。
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公开(公告)号：KR1020090118237A
公开(公告)日：2009-11-18
申请号：KR1020080043908
申请日：2008-05-13
Applicant: 재단법인서울대학교산학협력재단
IPC: H01L29/775 , H01L21/336
CPC classification number: H01L29/7613 , H01L29/4236 , H01L29/4983 , H01L29/66439 , H01L29/66621
Abstract: PURPOSE: A dual gate single electron transistor having a recess channel and a manufacturing method thereof are provided to reduce whole capacitance of a quantum dot by controlling a junction depth of source/drain. CONSTITUTION: A dual gate single electron transistor having a recess channel includes a substrate, a side gate, a control gate, a source region, a drain region, and a recess channel region. The substrate has a groove shape of a fixed depth. Two side gates(70) are formed in both sides of the groove. A first insulation film(42) is positioned between the two side gates. The control gate(81) is formed on each side gate. A second insulation film(43) is positioned between the control gates. The source region(91) and the drain region(92) are formed on the substrate. The groove is positioned between the source region and the drain region. The recess channel region surrounds the groove in between the source region and the drain region.
Abstract translation: 目的：提供具有凹槽通道的双栅单电子晶体管及其制造方法，以通过控制源极/漏极的结深来减小量子点的整体电容。 构成：具有凹槽的双栅单电子晶体管包括衬底，侧栅极，控制栅极，源极区域，漏极区域和凹陷沟道区域。 基板具有固定深度的凹槽形状。 两个侧门（70）形成在槽的两侧。 第一绝缘膜（42）位于两个侧门之间。 控制门81形成在每个侧门上。 第二绝缘膜（43）位于控制门之间。 源区域（91）和漏极区域（92）形成在基板上。 沟槽位于源极区域和漏极区域之间。 凹槽通道区域围绕源极区域和漏极区域之间的沟槽。
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