公开(公告)号：KR102003523B1

公开(公告)日：2019-07-24

申请号：KR1020120090179

申请日：2012-08-17

Applicant: 삼성전자주식회사

Inventor： 박상진 ,  윤보언 ,  한정남 ,  권기상 ,  최원상

IPC: H01L21/28 ,  H01L21/768

公开(公告)号：KR101850409B1

公开(公告)日：2018-06-01

申请号：KR1020120026721

申请日：2012-03-15

Applicant: 삼성전자주식회사

Inventor： 송명근 ,  고기형 ,  전하영 ,  윤보언 ,  한정남

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/401 ,  H01L21/823462 ,  H01L29/66545

Abstract: 듀얼게이트절연막을갖는반도체장치의제조방법이제공된다. 상기방법은, 제1 영역과제2 영역을포함하는기판을제공하고, 상기기판상에, 제1 두께를갖는제1 게이트절연막을형성하고, 상기기판상에, 상기제1 영역의상기제1 게이트절연막을노출하는제1 트렌치와상기제2 영역의상기제1 게이트절연막을노출하는제2 트렌치를포함하는층간절연막을형성하고, 상기층간절연막상 및상기제1 및제2 트렌치의바닥에희생막을형성하고, 상기희생막상에, 상기제2 영역의제2 트렌치를덮는마스크패턴을형성하고, 상기마스크패턴을식각마스크로상기제1 영역내의희생막을제거하여상기제1 트렌치의바닥의상기제1 게이트절연막을노출하는희생막패턴을형성하고, 상기제1 트렌치의바닥의상기제1 게이트절연막을제거하여기판을노출하고, 상기마스크패턴을제거하고상기희생막패턴을제거하고, 상기제1 트렌치의바닥에제2 두께를갖는제2 게이트절연막을형성하고, 상기제1 게이트절연막및 상기제2 게이트절연막상에게이트전극을형성하는것을포함한다.

公开(公告)号：KR101815527B1

公开(公告)日：2018-01-05

申请号：KR1020100097922

申请日：2010-10-07

Applicant: 삼성전자주식회사

Inventor： 박상진 ,  윤보언 ,  한정남

IPC: H01L29/78 ,  H01L21/336 ,  H01L27/092

CPC classification number: H01L29/0847 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/535 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: 반도체소자및 그제조방법이제공된다. 반도체소자는반도체기판상에게이트절연막을개재하여적층된금속게이트전극, 금속게이트전극양측의반도체기판상에배치된스페이서구조체들, 게이트전극양측의상기반도체기판내에형성된소오스/드레인영역및 소오스/드레인영역을덮는바닥부와바닥부로부터연장되어스페이서구조체의측벽일부분을덮는측벽부를포함하는식각정지패턴을포함하되, 식각정지패턴의측벽부의상면은금속게이트전극의상면아래에위치할수 있다.

公开(公告)号：KR101520457B1

公开(公告)日：2015-05-18

申请号：KR1020090011526

申请日：2009-02-12

Applicant: 삼성전자주식회사

Inventor： 김영옥 ,  한정남 ,  홍창기 ,  윤보언 ,  이근택 ,  김영후

IPC: H01L21/66

CPC classification number: H01L22/14

Abstract: 본발명은웨이퍼검사방법및 웨이퍼검사장치를제공하며, 이방법은, 소정의칩 영역에서금속함유막패턴의일 부분과접하도록전해액을공급하고, 상기금속함유막패턴의다른부분과전기적으로접하는제 1 전극과, 상기전해액과접하는제 2 전극사이의전기저항을측정함으로써, 상기측정된전기저항을이용하여상기금속함유막패턴측벽의부산물의양이나부식정도를알아낼수 있다. 이로써, 웨이퍼를조각내지않고도인라인방식으로웨이퍼를검사하는방법및 장치를구현할수 있다.

公开(公告)号：KR1020140103650A

公开(公告)日：2014-08-27

申请号：KR1020130017306

申请日：2013-02-19

Applicant: 삼성전자주식회사

Inventor： 박상진 ,  윤보언 ,  한정남 ,  권기상 ,  윤두성 ,  최원상

IPC: H01L21/02 ,  H01L21/306

CPC classification number: H01L21/67075 ,  H01L21/67017 ,  H01L21/6708

Abstract: Disclosed are a liquid chemical supplier for wet treatment and a wet treatment apparatus comprising the same. The liquid chemical supplier is only heated when performing the wet treatment process, not heated in the stand-by state, due to an in-line heater disposed on a liquid chemical supply line for supplying a liquid chemical mixture to a process chamber or a source supply line for supplying source materials constituting the liquid chemical mixture. Accordingly, the operational costs of the liquid chemical supplier can be reduced. On the other hand, the evaporation of the source materials is prevented by constituting the inside of a liquid chemical storage tank as a closed space and increasing the internal pressure. Accordingly, the usage time of the liquid chemical mixture can be increased and an amount of disposal can be reduced.

Abstract translation: 公开了一种用于湿处理的液体化学品供应商和包括其的湿式处理设备。 液体化学品供应商仅在执行湿处理过程时被加热，在待机状态下不被加热，这是由于设置在用于将液体化学混合物供应到处理室或源的液体化学品供应管线上的直列式加热器 用于供应构成液体化学混合物的源材料的供应线。 因此，液体化学品供应商的运营成本可以降低。 另一方面，通过将液体化学品储存器的内部构成为封闭空间并增加内部压力来防止源材料的蒸发。 因此，可以提高液体化学混合物的使用时间，并且可以减少处理量。

公开(公告)号：KR1020130104835A

公开(公告)日：2013-09-25

申请号：KR1020120026721

申请日：2012-03-15

Applicant: 삼성전자주식회사

Inventor： 송명근 ,  고기형 ,  전하영 ,  윤보언 ,  한정남

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/401 ,  H01L21/823462 ,  H01L29/66545

Abstract: PURPOSE: A method for manufacturing a semiconductor device including a dual gate insulation layer is provided to prevent the degradation of the reliability of the semiconductor device which includes gate insulation layers with different thicknesses on a high voltage area and a low voltage area. CONSTITUTION: A substrate (110) including a first area and a second area is provided. A first gate insulation layer (130) with a first thickness is formed on the substrate. An interlayer dielectric layer (140) including a first trench and a second trench is formed on the substrate. A second gate insulation layer (180) is formed on the bottom of the first trench of the first area. A high dielectric material (185) is formed on the first and second gate insulating layers. A gate electrode (192) is formed in the first trench and the second trench by planarizing the high dielectric material.

Abstract translation: 目的：提供一种制造包括双栅极绝缘层的半导体器件的方法，以防止在高电压区域和低电压区域上包括具有不同厚度的栅极绝缘层的半导体器件的可靠性劣化。 构成：提供包括第一区域和第二区域的基板（110）。 在基板上形成具有第一厚度的第一栅极绝缘层（130）。 在衬底上形成包括第一沟槽和第二沟槽的层间介质层（140）。 第一栅极绝缘层（180）形成在第一区域的第一沟槽的底部。 在第一和第二栅极绝缘层上形成高介电材料（185）。 通过平坦化高介电材料，在第一沟槽和第二沟槽中形成栅电极（192）。

公开(公告)号：KR1020130059028A

公开(公告)日：2013-06-05

申请号：KR1020110125108

申请日：2011-11-28

Applicant: 삼성전자주식회사

Inventor： 안경진 ,  윤보언 ,  한정남

IPC: H01L21/76

CPC classification number: H01L21/76229 ,  H01L21/0206 ,  H01L21/02065 ,  H01L21/0475 ,  H01L21/30604 ,  H01L21/30621 ,  H01L21/31055 ,  H01L21/31056 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76205 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/66545

Abstract: PURPOSE: A method for fabricating a semiconductor device is provided to improve product reliability by forming a thickness of a metal gate formed on an active which is the same as the thickness of a metal gate formed on a second element isolation layer. CONSTITUTION: A first element isolation layer and a second element isolation layer are formed in a semiconductor substrate(S100). A dry cleaning and a wet etching process are performed on the semiconductor substrate(S110). A transistor is formed on the semiconductor substrate(S120). [Reference numerals] (AA) Start; (BB) End; (S100) Form a first and a second element isolation layer on a semiconductor substrate; (S110) Dry-cleaning and wet-etching the semiconductor substrate; (S120) Form a transistor on the semiconductor substrate

Abstract translation: 目的：提供一种用于制造半导体器件的方法，通过形成与形成在第二元件隔离层上的金属栅极的厚度相同的在活性物上形成的金属栅极的厚度来提高产品的可靠性。 构成：在半导体衬底中形成第一元件隔离层和第二元件隔离层（S100）。 在半导体衬底上进行干法和湿式蚀刻处理（S110）。 晶体管形成在半导体衬底上（S120）。 （附图标记）（AA）开始; （BB）结束; （S100）在半导体衬底上形成第一和第二元件隔离层; （S110）半导体衬底的干式和湿法蚀刻; （S120）在半导体衬底上形成晶体管

公开(公告)号：KR1020120022464A

公开(公告)日：2012-03-12

申请号：KR1020100086072

申请日：2010-09-02

Applicant: 삼성전자주식회사

Inventor： 안경진 ,  박상진 ,  백재직 ,  윤보언 ,  한정남

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L21/02532 ,  H01L21/0262 ,  H01L21/3083 ,  H01L29/66545 ,  H01L29/66636 ,  H01L21/76232

Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to form compressive stress on a channel region of a PMOS(p-channel MOSFET(metal-oxide-semiconductor field-effect transistor)) by forming a SiGe(Silicon-Germanium) layer in a trench. CONSTITUTION: A gate electrode(120) is formed on a substrate(100). A spacer(140) is formed on a sidewall of the gate electrode. A first auxiliary trench(150) is formed by etching a certain area of the substrate exposed with the gate electrode and the spacer. A sacrificing layer(160) is formed on a lower surface of the first auxiliary trench. A second auxiliary trench is formed by laterally etching the sidewall of the first auxiliary trench.

Abstract translation: 目的：提供一种用于制造半导体器件的方法，通过在Si（Ge-Ge）层中形成SiGe（硅 - 锗）层，在PMOS（p沟道MOSFET（金属氧化物半导体场效应晶体管））的沟道区上形成压应力 一个沟槽 构成：在基板（100）上形成栅电极（120）。 间隔物（140）形成在栅电极的侧壁上。 第一辅助沟槽（150）通过蚀刻暴露于栅电极和间隔物的衬底的某一区域而形成。 牺牲层（160）形成在第一辅助沟槽的下表面上。 通过横向蚀刻第一辅助沟槽的侧壁形成第二辅助沟槽。

公开(公告)号：KR1020090105621A

公开(公告)日：2009-10-07

申请号：KR1020080031185

申请日：2008-04-03

Applicant: 삼성전자주식회사

Inventor： 엄대홍 ,  홍창기 ,  이근택 ,  강대혁 ,  한정남

IPC: H01L21/304

Abstract: PURPOSE: A method for cleaning a wafer and a device for performing the same are provided to remove the contaminant on the wafer by applying the ultrasound wave to the front surface of the wafer. CONSTITUTION: A wafer is immersed in a cleaning solution. An interval between the position for applying a first ultrasound wave and a first surface of the wafer is controlled(ST202). The first surface of the wafer is cleaned by applying the first ultrasound wave to the first surface of the wafer(ST204). The interval between the position for applying a second ultrasound wave and a second surface of the wafer are controlled(ST206). The second surface of the wafer is cleaned by applying the second ultrasound wave to the second surface of the wafer(ST208).

Abstract translation: 目的：提供清洁晶片的方法和用于执行晶片的装置，以通过将超声波施加到晶片的前表面来去除晶片上的污染物。 构成：将晶片浸入清洁溶液中。 控制用于施加第一超声波的位置与晶片的第一表面之间的间隔（ST202）。 通过将第一超声波施加到晶片的第一表面来清洁晶片的第一表面（ST204）。 控制用于施加第二超声波的位置与晶片的第二表面之间的间隔（ST206）。 通过将第二超声波施加到晶片的第二表面来清洁晶片的第二表面（ST208）。

公开(公告)号：KR1020090001377A

公开(公告)日：2009-01-08

申请号：KR1020070065704

申请日：2007-06-29

Applicant: 삼성전자주식회사

Inventor： 정병홍 ,  남정림 ,  박현 ,  정승필 ,  신상욱 ,  한정남 ,  장현석 ,  최호욱

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L21/76229 ,  H01L21/28141 ,  H01L21/31144 ,  H01L27/11521

Abstract: The method for forming the semiconductor device is provided to form the trench having the excellent lateral profile by etching the substrate using the aluminum oxide film pattern and the mask pattern as the etching mask. The insulating layer, the conductive film, and the aluminum oxide film and the mask are successively formed on the substrate(100). The aluminum oxide film is etched by using the mask as the etching mask. The preliminary aluminum oxide film pattern(128) is formed to expose the conductive film's surface in the first width. The side of the preliminary aluminum oxide film pattern is etched. The aluminum oxide film pattern is formed, exposing the conductive film surface in the second width which is broader than the first width. The conductive layer pattern(142), and the insulating layer pattern(144) and trench(148) are formed by using the mask and aluminum oxide film pattern as the etching mask.

Abstract translation: 提供了形成半导体器件的方法，通过使用氧化铝膜图案和掩模图案作为蚀刻掩模通过蚀刻衬底来形成具有优异横向轮廓的沟槽。 绝缘层，导电膜和氧化铝膜和掩模依次形成在基板（100）上。 通过使用掩模作为蚀刻掩模来蚀刻氧化铝膜。 形成初步氧化铝膜图案（128）以使第一宽度的导电膜的表面露出。 蚀刻初步氧化铝膜图案的一侧。 形成氧化铝膜图案，使导电膜表面暴露于比第一宽度宽的第二宽度。 通过使用掩模和氧化铝膜图案作为蚀刻掩模来形成导电层图案（142）和绝缘层图案（144）和沟槽（148）。