Abstract:
PURPOSE: A successive approximation AD converter is provided to correct digital output errors, increase the region of the dynamic operation of a signal converter, and improve the noise ratio of outputted signals by including two bits with the same size of capacitance as LSB(Least Significant Bit). CONSTITUTION: A first converting column(100) includes a plurality of capacitors and is connected to a first input terminal of a comparator(200). A second converting column(150) has the same configuration as the first converting column. 8 capacitors are connected to the second input terminal of the comparator. The comparator outputs a high or low output voltage to an SAR(Successive Approximation Register) logic unit of a controller(300) according to the differential voltage between the voltage of the first input terminal and the voltage of the second input terminal. The controller sets the digital signal to high or low level to control the switch of the capacitor and provides the set signal to the switch.
Abstract:
Provided are a dynamic element-matching method, a multi-bit Digital-to-Analog Converter (DAC), and a delta-sigma modulator with the multi-bit DAC and delta-sigma DAC with the multi-bit DAC. The dynamic element-matching method relates to preventing periodic signal components (in-band tones) from being generated from a delta-sigma modulator of a delta-sigma Analog-to-Digital Converter (ADC) and a multi-bit DAC used in a delta-sigma DAC. Unit elements are selected in a new sequence according to a simple algorithm every time that each of unit elements is selected once, and thus the unit elements are not periodically used. Consequently, it is possible to prevent in-band tones caused by a conventional Data Weighted Averaging (DWA) algorithm.
Abstract:
A voltage-controlled oscillator with wide frequency range is provided to increase the range of oscillation frequency by increasing variable capacitance by a plurality of MOS transistors connected to a LC resonance circuit. In a voltage-controlled oscillator, an LC resonance circuit(230) oscillates a frequency according to a control voltage and an amplifier circuit(250) amplifies the oscillation frequency. The LC resonance circuit includes a first and a second inductor, a variable capacitance unit, and a second variable capacitance(220). The first capacitance unit has a first and second varator which are connected with each other in parallel. The first variable capacitance has a first capacitance according to a first control voltage, and second variable capacitance has a firs and a second transistor which are connected with the varator in parallel and it has a second capacitance according to a second control voltage.
Abstract:
An algorithmic analog-to-digital converter is provided to minimize linearity restriction derived from a capacitor mismatch by adding two digital signals outputted through two different capacitors when one analog signal is inputted. An algorithmic analog-to-digital converter includes an SHA(Sample-and-Hold Amplifier)(10) sampling and holding an inputted analog voltage. Two flash ADCs(30) converts one inputted analog signal to two digital signals(n1,n2) through two different capacitor and outputs two digital signals. One MDAC(Multiplying Digital-to-Analog Converter)(50) amplifies a difference between an outputted voltage of the SHA and a reference voltage through two different capacitor according to the digital signal outputted from the flash ADC and outputs to the flash ADC again. A continuous multi-phase clock generating circuit(60) differentially outputs an operation clock frequency according to a required resolution.
Abstract:
본 발명은 재구성이 가능한 멀티밴드 멀티모드 무선 송수신기에 사용되는 LC공조 전압제어발진기(voltage-controlled oscillator:VCO)에 관한 것으로 광대역 멀티밴드의 주파수를 발생시키기 위해 커패시터 뱅크와 스위칭할 수 있는 인덕터가 내장된 구조이다. 본 발명의 적응성 에미터-축퇴 부성 저항셀을 내장한 LC공조 전압제어발진기에서 커패시터 뱅크에 의한 발진진폭의 불균형을 보상하기 위해 꼬리전류원 대신에 상기 적응성 에미터-축퇴 부성 저항셀을 사용하여 상기 꼬리전류원에 의한 상기 LC공조 전압제어발진기의 위상잡음 열화를 방지한다. 본 발명의 LC 공조 전압제어발진기는, 발진파의 주파수를 결정하는 인덕턴스 성분을 제공하기 위한 인덕턴스부; 발진파의 주파수를 결정하며 제어 비트에 따라 이산적으로 정해지는 커패시턴스 성분을 제공하기 위한 이산 커패시터 뱅크; 및 발진파의 진폭을 일정하게 하기 위해, 상기 제어 비트에 따라 이산적으로 결정되는 부(-)성 저항 성분을 제공하기 위한 이산 부성 저항셀을 포함하는 것을 특징으로 한다. 전압제어발진기, VCO, LC 발진기, 다중 대역 발진기, 꼬리전류원
Abstract:
A triple well p-type low voltage triggered ESD protection device is provided to perform an operation at a low trigger voltage, to minimize parasitic capacitance, and to obtain a fast response speed to an ESD pulse. A deep n-type well(30) is formed on a p-type substrate(20). An n-type well(40) and a p-type well(50) are formed within the deep n-type well. A bias applying region is formed to apply directly a bias voltage to the p-type well. The bias applying region is formed with a p+ diffusion region(80) which is formed at a junction side of the n-type well and the p-type well.
Abstract:
An LC resonance voltage controlled oscillator for a multiband with an adaptive negative resistance cell is provided to prevent the deterioration of phase noise and to sufficiently compensate for variation of oscillation amplitude. An LC resonance voltage controlled oscillator(300) for a multiband with an adaptive negative resistance cell includes an inductance unit(330), a discrete capacitor bank, and a discrete negative resistance cell(310). The inductance unit provides an inductance component determining the frequency of an oscillating wave. The discrete capacitor bank determines the frequency of the oscillating wave, and provides a capacitance component discretely determined according to a control bit. The discrete negative resistance cell provides a negative resistance component discretely determined by the control bit so as to make amplitude of the oscillating wave uniform.
Abstract:
A multiplying track-and-hold amplifier is provided to maximize efficiency of a signal process by using a compensation capacitor of a two-step amplifier as a hold capacitor. A multiplying track-and-hold amplifier processes two different signals for one period. The track-and-hold amplifier maintains a previous signal for a phase Phi1 and outputs a new input signal at a phase Phi2. Switches(SW1,SW1B) and sampling switches(SW3,SW3B) are switched on. Voltages(Vcp,Vcn) are sampled in Cs and CSB. Tracking switches(SW4,SW4B) and switches(SW6,SW6B) connected to an output terminal are switched off. A voltage of the output terminal maintains the last voltage of the phase Phi2. Amplifiers(A2,Cc,CCB) maintain an output function. The voltages(Vcn,Vcp) are applied to Cs and CSB through input switches(SW2,SW2B) at the phase Phi2.
Abstract:
본 발명은 반도체 집적회로(Integrated Circuit)에 적용되는 반도체 제어 정류기(Silicon Controlled Rectifier; SCR)를 이용한 정전기 방전(Electro-static discharge; ESD) 보호 회로에 관한 것으로, 제 1 웰 및 제 2 웰이 형성된 반도체 기판; 상기 제 1 웰의 상부에 형성된 제 1 및 제 2 고농도 이온주입 영역; 상기 제 2 웰의 상부에 형성된 제 3 및 제 4 고농도 이온주입 영역; 상기 제 1 웰 및 제 2 웰 계면에 형성된 제 5 고농도 이온주입 영역; 상기 제 5 고농도 이온주입 영역 일측의 상기 제 2 웰 상부에 형성된 제 6 고농도 이온주입 영역; 상기 제 6 고농도 이온주입 영역에 드레인이 접속되고, 상기 제 1 및 제 2 고농도 이온주입 영역에 소스가 접속되고, 게이트가 저항을 통해 상기 제 1 및 제 2 고농도 이온주입 영역에 접속된 제 1 과부하 방지수단; 및 상기 제 5 고농도 이온주입 영역에 드레인이 접속되고, 상기 제 3 및 제 4 고농도 이온주입 영역에 소스가 각각 접속되고, 게이트가 저항을 통해 상기 제 3 및 제 4 고농도 이온주입 영역에 접속된 제 2 과부하 방지수단을 포함한다. 정전기 방전(ESD), 보호 회로, 반도체 제어 정류기(SCR), 제너 접합 다이오드, 트리거 전압
Abstract:
본 발명은 위상고정루프를 이용한 Fractional-N 주파수 합성기에 관한 것이다. 본 발명에 따른 주파수 합성기는 고차 시그마-델타 변조기, 펄스-스왈로우 방식의 다중모드 분주기, 저위상잡음을 갖는 부궤환 방식의 LC-공조 전압제어발진기를 포함한다. 이러한 구성에 의해, 본 발명의 시그마-델타 Fractional-N 주파수 합성기는 시그마-델타에 의한 노이즈 쉐이핑과 우수한 스퓨리어스 억제 기능을 가진다. fractional-N 주파수 합성기, 위상고정루프, 시그마-델타, 펄스-스왈로우, 다중모드 분주기, LC-공조 전압제어발진기