公开(公告)号：KR1020100070932A

公开(公告)日：2010-06-28

申请号：KR1020080129686

申请日：2008-12-18

Applicant: 한국전자통신연구원

Inventor： 정우석 ,  유민기 ,  정승묵 ,  황치선 ,  추혜용

IPC: G06F3/042 ,  B32B27/00 ,  H01B5/14

CPC classification number: G06F3/044 ,  B32B2457/208 ,  G06F2203/04103 ,  H01B5/14

Abstract: PURPOSE: A touch panel film and a method for preparing the same are provided to enhance durability without influence on the transmittance thereof by using a metallic seed layer to a transparent conductive layer. CONSTITUTION: A metallic seed layer is formed on a transparent plastic substrate(S11), and the transparent conductive layer is formed on the metallic seed layer(S12). The transparent conductive layer is heat-treated(S13), and all the processes are processed under 150°C. A buffer layer is made of an oxide insulator and is formed on the transparent substrate before forming the metallic seed layer. A protection layer is formed by coating and hardening a hardening resin at the lower portion of the transparent substrate.

Abstract translation: 目的：提供触摸屏膜及其制备方法，以通过将金属种子层用于透明​​导电层来提高耐久性而不影响其透光率。 构成：在透明塑料基板上形成金属种子层（S11），在金属种子层上形成透明导电层（S12）。 对透明导电层进行热处理（S13），所有工序在150℃以下进行。 缓冲层由氧化物绝缘体制成，并且在形成金属种子层之前形成在透明基板上。 通过在透明基板的下部涂覆硬化树脂而形成保护层。

公开(公告)号：KR1020100045600A

公开(公告)日：2010-05-04

申请号：KR1020080104592

申请日：2008-10-24

Applicant: 한국전자통신연구원

Inventor： 정승묵 ,  정우석 ,  유민기 ,  황치선 ,  추혜용

IPC: H01L21/316

CPC classification number: H01L21/02192 ,  H01L21/2855 ,  H01L29/7869

Abstract: PURPOSE: A composition for a p-type oxide semiconductor thin film and a method for manufacturing the p-type oxide semiconductor thin film are provided to simplify a manufacturing process by simultaneously depositing a rare earth-based element doped-zinc oxide and a copper metal. CONSTITUTION: A zinc oxide is doped with a rare earth-based element in order to form a first target(S11). A second target which is based on a copper metal is formed(S12). The first target and the second target are simultaneously deposited to form an oxide semiconductor thin film(S13). The rare earth-based element is selected from a group which includes praseodymium(Pr), dysprosium(Dy), europium(Eu) and erbium(Er).

Abstract translation: 目的：提供一种用于p型氧化物半导体薄膜的组合物和用于制造p型氧化物半导体薄膜的方法，以通过同时沉积稀土类元素掺杂的氧化锌和铜金属来简化制造工艺 。 构成：为了形成第一靶，掺杂有稀土元素的氧化锌（S11）。 形成基于铜金属的第二靶（S12）。 同时沉积第一靶和第二靶以形成氧化物半导体薄膜（S13）。 稀土类元素选自镨（Pr），镝（Dy），铕（Eu），铒（Er）等。

公开(公告)号：KR1020100028347A

公开(公告)日：2010-03-12

申请号：KR1020080087342

申请日：2008-09-04

Applicant: 한국전자통신연구원

Inventor： 정우석 ,  유민기 ,  정승묵 ,  황치선 ,  추혜용

IPC: H01L21/20 ,  H01L21/265 ,  H01L29/786

CPC classification number: H01L21/02554 ,  H01L21/324 ,  H01L29/7869

Abstract: PURPOSE: A method for manufacturing a metal-doped transparent conductive oxide thin film and a thin film transistor using the same are provided to drive the thin film transistor at a low voltage by adjusting the resistance distribution of the transparent conductive oxide thin film. CONSTITUTION: Metal and oxide are simultaneously deposited on a substrate. An oxide film is formed. The metal is doped into the oxide layer. The metal is selected from a group including Mo, Ti, Cu, Sr, Ge, Mg, Y, Zr, B, V, Ta, Tl, Ir, Te, Sb, Cr, Fe, Co, Ru, Ag, Au, Pt, Me, Ni, Sn, Bi, Al, Ga and In. The oxide is selected from a group including ZnO, SnO2, Zn-Sn-O, Ga2O3 and In2O3.

Abstract translation: 目的：提供一种用于制造掺杂金属的透明导电氧化物薄膜和使用其的薄膜晶体管的方法，以通过调节透明导电氧化物薄膜的电阻分布来驱动低电压的薄膜晶体管。 构成：金属和氧化物同时沉积在基底上。 形成氧化膜。 金属被掺杂到氧化物层中。 金属选自Mo，Ti，Cu，Sr，Ge，Mg，Y，Zr，B，V，Ta，Tl，Ir，Te，Sb，Cr，Fe，Co，Ru，Ag，Au， Pt，Me，Ni，Sn，Bi，Al，Ga和In。 氧化物选自ZnO，SnO 2，Zn-Sn-O，Ga 2 O 3和In 2 O 3。

公开(公告)号：KR100938675B1

公开(公告)日：2010-01-25

申请号：KR1020070132724

申请日：2007-12-17

Applicant: 한국전자통신연구원

Inventor： 신재헌 ,  황치선 ,  유민기 ,  정우석 ,  추혜용

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: 본 발명은 박막 트랜지스터의 소스-드레인 전류 모델링 방법에 관한 것으로, 본 발명의 일실시 예에 따른 박막 트랜지스터의 소스-드레인 전류 모델링 방법은, 표본 입력 값 및 표본 출력 값을 포함하는 표본 데이터를 입력받는 단계; 상기 표본 데이터에 상응하여 모델링 변수를 조정하는 단계; 상기 조정된 모델링 변수에 상응하여 전류 모델 값을 계산하는 단계; 상기 계산된 전류 모델 값과 상기 표본 출력 값의 차이 값이 미리 설정된 기준 값보다 작은 경우에는 상기 조정된 모델링 변수를 전류 모델에 적용하여 전류 모델을 피팅(fitting)하는 단계; 상기 피팅된 전류 모델에 실제 입력 데이터를 입력하는 단계; 및 상기 실제 입력 데이터에 상응하여 결과치를 출력하는 단계를 포함하되, 상기 전류 모델은 식(I
DS = I
leak + ( 1/I
b + 1/I
a )
-1 )에 의하여 드레인-소스 전류(I
DS )를 계산한다. 여기서, I
leak 는 박막 트랜지스터의 누설 전류, I
b 는 문턱 전압(threshold voltage) 이하의 영역에서 계산되는 소스-드레인 전류 값인 제 1 전류 값, I
a 는 문턱 전압 이상의 영역에서 계산되는 소스-드레인 전류 값인 제 2 전류 값이다.
상기와 같은 본 발명에 의하면, 산화물 TFT 뿐만 아니라 비결정질 실리콘 TFT 및 유기 TFT 에도 적용될 수 있는 정밀한 전류 모델을 제공할 수 있는 이점이 있다.
TFT 모델, 드레인-소스 전류, 산화물 TFT

公开(公告)号：KR1020100006519A

公开(公告)日：2010-01-19

申请号：KR1020080071163

申请日：2008-07-22

Applicant: 한국전자통신연구원

Inventor： 조두희 ,  박상희 ,  황치선 ,  추혜용 ,  조경익 ,  양신혁 ,  변춘원 ,  박은숙 ,  권오상 ,  유민기 ,  신재헌 ,  정우석 ,  정승묵 ,  이정익

IPC: C04B35/00 ,  H01B1/08 ,  H01L21/336 ,  H01L29/78

CPC classification number: C04B35/00 ,  H01B1/08 ,  H01L21/02554 ,  H01L21/02565 ,  H01L29/78693

Abstract: PURPOSE: An oxide semiconductor thin film composition is provided to obtain stable and transparent oxide semiconductor thin film having high mobility through low temperature process. CONSTITUTION: An oxide semiconductor thin film composition is amorphous state containing aluminum-containing oxide, zinc-containing oxide, indium-containing oxide, and tin-containing oxide. The ratio of the metal components is 30-95at% of zinc, 1-65at% of indium, 1-50at% of tin and remaining amount of aluminum.

Abstract translation: 目的：提供氧化物半导体薄膜组合物以获得通过低温处理具有高迁移率的稳定且透明的氧化物半导体薄膜。 构成：氧化物半导体薄膜组合物是含有含氧氧化物，含锌氧化物，含铟氧化物和含锡氧化物的非晶态。 金属成分的比例为锌的30-95原子％，铟的1-65原子％，锡的1-50原子％和铝的剩余量。

公开(公告)号：KR1020090099140A

公开(公告)日：2009-09-22

申请号：KR1020080024208

申请日：2008-03-17

Applicant: 한국전자통신연구원

Inventor： 박상희 ,  황치선 ,  변춘원 ,  양신혁 ,  이정익 ,  조두희 ,  신재헌 ,  유민기 ,  윤성민 ,  정우석 ,  권오상 ,  박은숙 ,  추혜용

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L21/02554

Abstract: A manufacturing method of a ZnO TFT is provided to reduce a defect inside a semiconductor thin film by controlling a deposition temperature after selecting oxygen plasma or ozone as oxygen precursor. A ZnO semiconductor film(30) is formed on a substrate(10) through an atomic layer deposition method using Zn precursor and ozone at a temperature of 250~350°C or Zn precursor and oxygen plasma at a temperature of 150~250°C. An insulation film(40) is formed on a top part of the ZnO semiconductor film through the atomic layer deposition method using the oxygen precursor selected from ozone or water at a temperature less than 250°C. A gate electrode(50) is formed on a top part of the insulation film. The ZnO semiconductor film has thickness of 5~40nm. The substrate is a substrate in which a source/drain electrode(20) is formed and a substrate in which the gate electrode and the insulation film are formed.

Abstract translation: 提供ZnO薄膜晶体管的制造方法，通过在选择氧等离子体或臭氧作为氧前体后控制沉积温度来减少半导体薄膜内的缺陷。 在250〜350℃的温度下，使用Zn前体和臭氧，在150〜250℃的温度下，通过Zn前体和氧等离子体，通过原子层沉积法在基板（10）上形成ZnO半导体膜（30） 。 通过使用在低于250℃的温度下使用选自臭氧或水的氧前体的原子层沉积方法，在ZnO半导体膜的顶部上形成绝缘膜（40）。 在绝缘膜的顶部形成有栅电极（50）。 ZnO半导体膜的厚度为5〜40nm。 基板是形成源极/漏极（20）的基板和形成有栅电极和绝缘膜的基板。

公开(公告)号：KR1020090065893A

公开(公告)日：2009-06-23

申请号：KR1020070133435

申请日：2007-12-18

Applicant: 한국전자통신연구원

Inventor： 유민기 ,  박상희 ,  정우석 ,  황치선

IPC: G02F1/13 ,  G02F1/1343

CPC classification number: G02F1/1303 ,  C03C17/42 ,  G09G2320/0233 ,  H01L31/1884

Abstract: A transparent conductive film etching method is provided to form a transparent conductive film pattern having superior step coverage and reduce the area of a TFT through minute patterning. A functional film having durability for etching on a transparent conductive film is formed(101). The transparent conductive film is etched by using photoresist(102). The photoresist is removed(103). The functional film is removed(104). The photoresist is removed by using chemical substance as acetone. The functional film is removed by performing etching during 3 to 5 seconds using etching solution for etching the transparent conductive film.

Abstract translation: 提供透明导电膜蚀刻方法以形成具有优异的台阶覆盖率的透明导电膜图案，并通过微小图案化来减小TFT的面积。 形成了对透明导电膜进行蚀刻的耐久性的功能膜（101）。 通过使用光致抗蚀剂（102）来蚀刻透明导电膜。 去除光致抗蚀剂（103）。 去除功能膜（104）。 通过使用化学物质作为丙酮除去光致抗蚀剂。 通过使用用于蚀刻透明导电膜的蚀刻溶液在3至5秒内进行蚀刻来去除功能膜。

公开(公告)号：KR100881954B1

公开(公告)日：2009-02-06

申请号：KR1020070114365

申请日：2007-11-09

Applicant: 한국전자통신연구원

Inventor： 정우석 ,  황치선 ,  유민기

IPC: H01L21/203

CPC classification number: C23C14/0047 ,  C23C14/3464

Abstract: A reactive sputtering deposition device capable of reducing temperature of sputtering deposition process is provided to improve uniformity of a thin film deposition and step coverage by increasing ionization rate of reactive gas with inductively coupled plasma. A plasma gas is flowed inside a chamber(110) through an inlet(140). A gas used in reactive sputtering deposition is exhausted outside the chamber through an outlet(150). An inductively coupled plasma generator(120) is positioned on the chamber, ionizes a reactive gas, and flows the ionized gas into the chamber. At least one or more sputter gun(130) is positioned in a side of the chamber, and supports a target.

Abstract translation: 提供能够降低溅射沉积工艺温度的反应性溅射沉积装置，通过增加电感耦合等离子体的反应气体离子化速率来提高薄膜沉积和台阶覆盖的均匀性。 等离子体气体通过入口（140）在室（110）内流动。 用于反应溅射沉积的气体通过出口（150）在室外排出。 电感耦合等离子体发生器（120）位于室上，电离反应气体，并将电离气体流入腔室。 至少一个或多个溅射枪（130）位于腔室的一侧，并且支撑靶。

公开(公告)号：KR1020080050989A

公开(公告)日：2008-06-10

申请号：KR1020070084717

申请日：2007-08-23

Applicant: 한국전자통신연구원

Inventor： 최성율 ,  유민기 ,  정후영

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: G11C13/0007 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/51 ,  G11C2213/55 ,  H01L45/10 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/141

Abstract: A memory device of a trap-controlled space charge limit current and a manufacturing method thereof are provided to effectively control charge trap distribution in a dielectric thin film by using a diffusion barrier layer and an inner diffusion barrier layer. A diffusion barrier layer(220) for an electrode-dielectric thin film is formed on the upper surface of a bottom electrode(210). A dielectric thin film(230) is formed on the upper portion of the diffusion barrier layer, and is composed of plural layers having different charge trap density. A top electrode(240) is formed on the upper portion of the dielectric thin film. An inner diffusion barrier layer(250) for preventing shift of charge tap is formed between the layers of the dielectric thin film.

Abstract translation: 提供陷阱控制空间电荷限制电流的存储器件及其制造方法，以通过使用扩散阻挡层和内部扩散阻挡层来有效地控制电介质薄膜中的电荷陷阱分布。 用于电极 - 电介质薄膜的扩散阻挡层（220）形成在底部电极（210）的上表面上。 介电薄膜（230）形成在扩散阻挡层的上部，由具有不同电荷陷阱密度的多个层组成。 顶部电极（240）形成在电介质薄膜的上部。 在电介质薄膜的层之间形成用于防止电荷抽头移动的内扩散阻挡层（250）。

公开(公告)号：KR1020070058939A

公开(公告)日：2007-06-11

申请号：KR1020060044063

申请日：2006-05-17

Applicant: 한국전자통신연구원

Inventor： 최성율 ,  유민기 ,  김안순 ,  아칠성 ,  유한영

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L29/4234 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/792

Abstract: A method device including a dielectric thin film is provided to simplify the structure of a memory device and embody integration of the memory device by using a dielectric thin film having a simple structure in which a plurality of dielectric layers are stacked. At least one dielectric thin film(130) is formed on a lower electrode(120), including a plurality of dielectric layers having different charge trap densities. An upper electrode(125) is formed on the dielectric thin film. Different space-charge limit currents flow through the dielectric thin film according to the charge trap density, controlled according to the impurities added to the dielectric thin film.

Abstract translation: 提供一种包括电介质薄膜的方法装置，以简化存储器件的结构，并且通过使用具有堆叠多个电介质层的简单结构的电介质薄膜来实现存储器件的集成。 至少一个电介质薄膜（130）形成在下电极（120）上，包括具有不同电荷陷阱密度的多个电介质层。 在电介质薄膜上形成上电极（125）。 不同的空间电荷极限电流根据电荷陷阱密度流过电介质薄膜，根据添加到电介质薄膜中的杂质控制。