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公开(公告)号：DE2532149A1
公开(公告)日：1976-03-04
申请号：DE2532149
申请日：1975-07-18
Applicant: IBM
Inventor： BOSSEN DOUGLAS CRAIG , HSIAO MU-YUE , PATEL ARVIND MOTIBHAI
Abstract: This specification describes an error correction system for a high density memory made up of a number of monolithic wafers each containing a plurality of arrays that are addressed thru circuitry and wiring contained on that wafer. The storage bits on the wafers are functionally divided into a number of blocks each containing a plurality of words. The words of each block are on several wafers with each word made up of a plurality of arrays on a single array wafer. Each word in a block is protected by a similar error correction double multiple error detection code. The block is further protected by two additional check words made up using a b-adjacent code. Each byte in the check words protects one byte position of the words of the block. When a single error is detected in any word by the SEC-MED code the code corrects the error. If a multiple error is detected, the multiple error signal points to the word in error to be corrected by the b-adjacent code check words.
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公开(公告)号：DE2425823A1
公开(公告)日：1975-01-02
申请号：DE2425823
申请日：1974-05-28
Applicant: IBM
Inventor： BOSSEN DOUGLAS CRAIG , HONG SE JUNE , HSIAO MU-YUE , PATEL ARVIND MOTIBHAI
Abstract: Errors in code words fetched from memory or utilized in some other device are detected by apparatus distributed throughout the memory and then corrected. Illustratively, a 72-bit parallel code word, comprising a 64-bit information portion and an 8-bit check portion is fetched from the memory. The check bit generator consists of 8 identical modular units which, in the case of use in a memory, can be located at different locations within the memory. The identical modular units are connected in accordance with connections determined by an H matrix. The H matrix is partitioned into eight equal sections associated with eight information bits forming a byte and a single check bit. The rows of each partition or section are cyclically permutated from section to section. For example, the first row of the first section becomes the second row of the second section, etc. Each partition of the H matrix contains the same number of 1's and each row within a partition is part of a different code group. Each of the identical modular arrangements contains a logic circuit grouping. The input information byte bits are connected to the circuits of the logic grouping so as to produce as circuit outputs the parities of the part of the code groups in the partition or section associated with the module. The identical modular units also contain circuitry to receive the partial code groups parities from the other modular units concerned with the same code group. These partial code group parities and the partial code group parity of the respective module are combined to provide the check bit for the particular module. The partial code group parity outputs from the module are transmitted to the successive other modules to form the partial code group parity inputs for the respective modules. After the information has been utilized such as writing in storage, the information bits and check bits are read into an error detector which compares the check bits generated from the received information bits with the received check bits. An error locator analyzes any mismatch to determine the location of an error. An error corrector then corrects any information or check bit which is identified as incorrect by the error locator. The error detector can consist of the same identical modular units as the check bit generator.
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公开(公告)号：DE2421112A1
公开(公告)日：1975-01-02
申请号：DE2421112
申请日：1974-05-02
Applicant: IBM
Inventor： BOSSEN DOUGLAS CRAIG , HSIAO MU-YUE , PATEL ARVIND MOTIBHAI
Abstract: 1440285 Error correction INTERNATIONAL BUSINESS MACHINES CORP 24 April 1974 [4 June 1973] 18002/74 Heading G4A Data is stored on a plurality of independently accessible storage units, e.g. magnetic tape cartridges, and check bits, each of which is a function of a corresponding bit from each data storage unit, are stored on a check unit which may be used, in the event of a catastrophic loss of data on one of the data storage units and detected by an error checking facility associated with that unit, to restore the data on that unit. Extension of the system to include more than one check unit, each of which stores the check bits for one position of a Hamming code, is also mentioned. In normal operation, one of the data storage units is selected and data thereon is updated by read before write heads 15, 21. The difference e jk between each old bit and the corresponding new bit is EXORed with the corresponding old parity bit p k from the check unit to update the parity bits. The parity bits are initially recorded by successively (or simultaneously) reading the data storage units to record the modulo 2 sums of the corresponding bits, and data restoration is similar reading from the good data storage units and the check unit.
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公开(公告)号：SG46485A1
公开(公告)日：1998-02-20
申请号：SG1996005030
申请日：1990-02-02
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means (Fig. 2) for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号：DE69029539T2
公开(公告)日：1997-07-17
申请号：DE69029539
申请日：1990-05-10
Applicant: IBM
Inventor： BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , HSIAO MY-YUE
Abstract: An error correction coding system employs a single check symbol from an arbitrary sequence of information symbols to provide single error correction at the symbol level. The sequence of information symbols may in fact also be arbitrarily long. The coding system of the present invention provides both a method and apparatus for encoding the check symbol and a method and apparatus for error correction based upon the single coded symbol character. The system is particularly applicable for use in conjunction with bar code recognition systems but is in fact applicable to a broad range of coding systems, including optical character recognition and ordinary alphanumeric codes.
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Patent Agency Ranking
公开(公告)号：DE69029539D1
公开(公告)日：1997-02-13
申请号：DE69029539
申请日：1990-05-10
Applicant: IBM
Inventor： BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , HSIAO MY-YUE
Abstract: An error correction coding system employs a single check symbol from an arbitrary sequence of information symbols to provide single error correction at the symbol level. The sequence of information symbols may in fact also be arbitrarily long. The coding system of the present invention provides both a method and apparatus for encoding the check symbol and a method and apparatus for error correction based upon the single coded symbol character. The system is particularly applicable for use in conjunction with bar code recognition systems but is in fact applicable to a broad range of coding systems, including optical character recognition and ordinary alphanumeric codes.
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公开(公告)号：NZ232466A
公开(公告)日：1992-08-26
申请号：NZ23246690
申请日：1990-02-09
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means (Fig. 2) for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号：AU623490B2
公开(公告)日：1992-05-14
申请号：AU4939390
申请日：1990-02-09
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO , LO TIN-CHEE
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号：DE2456709A1
公开(公告)日：1975-07-10
申请号：DE2456709
申请日：1974-11-30
Applicant: IBM
Inventor： BOSSEN DOUGLAS CRAIG , CORDI VINCENT ANTHONY , GLICK ELLIS WILLIAM , HSIAO MU-YUE , SHIFFRIN BARRY NORMAN
Abstract: An error correction and detection circuit includes a modular encoder that provides the minimum number of check bits for encoding a particular number of data bits. Means is provided for combining several units to produce the minimum number of code bits when a larger data word is to be encoded. A storage hierarchy system using this error correction circuit is also disclosed.
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公开(公告)号：GB1287387A
公开(公告)日：1972-08-31
申请号：GB1576171
申请日：1971-05-19
Applicant: IBM
Inventor： BOSSEN DOUGLAS CRAIG , HSIAO MU-YUE
Abstract: 1287387 Error correction-systems INTERNATIONAL BUSINESS MACHINES CORP 19 May 1971 [28 Sept 1970] 15761/71 Heading G4A A syndrome is computed from a code word including check bits, the syndrome is transformed successively through a succession of values, a gate responsive to a predetermined value senses the succession of syndrome values, and a code word bit, in a position corresponding to the number of successive values counted when the gate responds, is inverted to correct an error. In the described embodiment a shortened Bose-Chaudhuri code word containing 15 check bits and 64 data bits is fetched from memory and is entered in a ring counter 114 having a connection from the 00 bit stage 116 to the 78 bit stage 118. An exclusive OR tree syndrome computer 122 derives a 15-bit syndrome by modulo 2 addition of groups of bits. If no error is present the syndrome is all zeros, and a linear feedback shift register 126 arranged according to the generator polynomial of the check bits is successively shifted left so that if an error syndrome is present successive patterns of the syndrome matrix are generated by successive shifts. The register 126 feeds a bank of recognition gates 154 of which a first G oo is used for single error correction and the remainder G 01 -G 78 for double error correction. If two errors are present, the gate corresponding to the difference between the indices of the two erroneous bits responds when the first erroneous bit is in stage 116 of ring counter 114, and a second response is subsequently obtained from G oo , after correction of the first bit, when the second erroneous bit reaches stage 116. The OR'ed outputs of gates 154 are fed to correction gates 158, 159. The number of shifts made is counted at 164, and after 79 shifts, timing gate 162 is closed and data read-out gate 166 is opened. For faster operation, the output of syndrome computer 122 may be connected to conventional circuits for correcting single errors and detecting double errors, only the detected double errors being corrected by the above shift register circuit.
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