公开(公告)号：WO2007027813A3

公开(公告)日：2007-12-06

申请号：PCT/US2006033924

申请日：2006-08-30

Applicant: IBM ,  HSU LOUIS C ,  CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  RADENS CARL J ,  WONG KEITH KWONG HON ,  YANG CHIH-CHAO

Inventor： HSU LOUIS C ,  CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  RADENS CARL J ,  WONG KEITH KWONG HON ,  YANG CHIH-CHAO

IPC: H01P1/10

CPC classification number: H01H50/005 ,  H01H2050/007 ,  Y10T29/4902 ,  Y10T29/49105 ,  Y10T29/49147

Abstract: A MEM switch is described having a free moving element (140) within in micro-cavity (40), and guided by at least one inductive element. The switch consists of an upper inductive coil (170); an optional lower inductive coil (190), each having a metallic core (180,200) preferably made of permalloy; a micro-cavity (40); and a free-moving switching element (140) also made of magnetic material. Switching is achieved by passing a current through the upper coil, inducing a magnetic field in the coil element. The magnetic field attracts the free-moving magnetic element upwards, shorting two open wires (M_I M_r) and thus, closing the switch. When the current flow stops or is reversed, the free-moving magnetic element drops back by gravity to the bottom of the micro-cavity and the wires open. When gravity cannot be used, a lower coil becomes necessary to pull the free-moving switching element back and holding it at its original position.

Abstract translation: 描述了一种MEM开关，其具有在微腔（40）内的自由移动元件（140），并由至少一个电感元件引导。 开关由上部感应线圈（170）组成; 可选的下感应线圈（190），每个具有优选由坡莫合金制成的金属芯（180,200） 微腔（40）; 以及也由磁性材料制成的自由移动的开关元件（140）。 通过使电流通过上部线圈来实现切换，从而在线圈元件中产生磁场。 磁场向上吸引自由移动的磁性元件，使两根开放的导线（M_I M_r）短路，从而闭合开关。 当电流停止或反转时，自由移动的磁性元件通过重力返回到微腔的底部并且电线打开。 当不能使用重力时，需要下部线圈将自由移动的开关元件拉回并将其保持在其原始位置。

公开(公告)号：DE112023002938T5

公开(公告)日：2025-05-15

申请号：DE112023002938

申请日：2023-09-05

Applicant: IBM

Inventor： SENAPATI BISWANATH ,  MUNETOH SEIJI ,  LANZILLO NICHOLAS ANTHONY ,  CLEVENGER LAWRENCE A ,  BURR GEOFFREY ,  HOSOKAWA KOHJI

IPC: H10B63/10 ,  H01L21/768 ,  H01L23/52

Abstract: Eine IC-Speichereinheit enthält ein Substrat und ein Array von Speicherzellen auf dem Substrat. Jede Speicherzelle enthält wenigstens einen Speicherzellentransistor in einer Schicht der Einheit benachbart zu dem Substrat. In der gleichen Schicht enthält die Einheit ferner eine Mehrzahl von Nebenschlusstransistoren. Die Einheit enthält ferner eine vergrabene Metall-Signalschiene, die zwischen dem Array von Speicherzellen und der Mehrzahl von Nebenschlusstransistoren in einer vergrabenen Schicht angeordnet ist, die unter den Transistoren in dem Substrat eingebettet ist. Die Einheit enthält ferner Einzelschicht-Durchkontaktierungen, die in der gleichen Schicht wie die Transistoren angeordnet sind und die Speicherzellentransistoren durch die vergrabene Metall-Signalschiene elektrisch mit den Nebenschlusstransistoren verbinden.

公开(公告)号：JP2008277807A

公开(公告)日：2008-11-13

申请号：JP2008102183

申请日：2008-04-10

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CLEVENGER LAWRENCE A ,  EDELSTEIN DANIEL C ,  BREYTA GREGORY ,  COLBURN MATTHEW EARL ,  SHOM PONOTH

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5222 ,  H01L21/7682 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which reduces cross-talk between conducting lines for wiring. SOLUTION: A method of forming a cavity in a semiconductor device 300 comprises a step for depositing an anti-nucleating layer 318 on the interior surface of the cavity in an ILD layer of the semiconductor device. This anti-nucleating layer prevents a subsequently-deposited dielectric layer from being formed in the cavity. By preventing the formation of these layers, capacitance is reduced, thereby resulting in improved semiconductor performance. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种减少用于布线的导线之间的串扰的半导体器件。 解决方案：在半导体器件300中形成腔的方法包括在半导体器件的ILD层中的空腔的内表面上沉积抗成核层318的步​​骤。 该防成核层防止在空腔中形成随后沉积的介电层。 通过防止这些层的形成，电容降低，从而提高半导体性能。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2004080036A

公开(公告)日：2004-03-11

申请号：JP2003292574

申请日：2003-08-12

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CLEVENGER LAWRENCE A ,  FENG GEORGE C ,  HARPER JAMES M E ,  LEWIS L SUU

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/4991 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/6659

Abstract: PROBLEM TO BE SOLVED: To provide a method for improving performance in a microelectronic circuit. SOLUTION: A method and a structure for an integrated circuit transistor include a gate conductor having a first conductive material and a second material. The structure has a spacer that is adjacent to the gate conductor and cannot be deformed, and the gap between the gate conductor and the spacer. The first conductive material can be polysilicon, and the second material can be either metal or a polymer. The second material operates as a place holder for the gap. An environmental gas is contained by the gap, and resistance in the gate conductor is reduced. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2004080031A

公开(公告)日：2004-03-11

申请号：JP2003288276

申请日：2003-08-06

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CLEVENGER LAWRENCE A ,  LOUIS L SHEW ,  WONG KWONG HON

IPC: H01L27/10 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/06 ,  H01L27/108 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L21/28194 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28114 ,  H01L27/0629 ,  H01L27/10805 ,  H01L27/1085 ,  H01L27/10885 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66545

Abstract: PROBLEM TO BE SOLVED: To offer an integrated circuit structure comprising a pair of capacitors, which respectively have metal plates separated by an insulator, and a metal-gate semiconductor transistor which is electrically connected to the capacitors.
SOLUTION: Each metal gate of a transistor and one of the metal plates of each capacitor have the same metal level in an integrated circuit structure. A more detailed description is that each capacitor described above comprises a vertical capacitor which has an upper metal plate vertically above a lower metal plate, and each metal gate of the transistor and the upper metal plate of each capacitor have the same metal level in the integrated circuit structure.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2003023155A

公开(公告)日：2003-01-24

申请号：JP2002127052

申请日：2002-04-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： CLEVENGER LAWRENCE A ,  HSU LOUIS L ,  RADENS CARL J ,  SHEPARD JOSEPH F JR

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L21/28176 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/28194 ,  H01L29/512 ,  H01L29/517

Abstract: PROBLEM TO BE SOLVED: To provide a MOSFET(metal oxide semiconductor field effect transistor) and a method for manufacturing the MOSFET capable of eliminating the overlap of a gate dielectric and a source/drain region with high reliability.
SOLUTION: This method for manufacturing a MOSFET comprises the process of patterning a gate laminate constituted of a gate dielectric 20 arid a gate conductor 30 formed on a substrate 10, and the process of modifying the gate dielectric 20 beneath the gate dielectric 30 so that the gate dielectric 20 can have a central portion and a modified dielectric region 70 adjacent to the central portion. The modified dielectric region 70 has a lower dielectric constant than that of the gate dielectric 20, and the central portion is shorter than the gate conductor 30.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种MOSFET（金属氧化物半导体场效应晶体管）以及能够以高可靠性消除栅极电介质和源极/漏极区域的重叠的MOSFET的制造方法。 解决方案：用于制造MOSFET的方法包括对由栅极电介质20和形成在衬底10上的栅极导体30构成的栅极叠层的图案化以及在栅极电介质30下面改变栅极电介质20的工艺， 栅极电介质20可以具有与中心部分相邻的中心部分和改进的电介质区域70。 改性电介质区域70具有比栅极电介质20低的介电常数，并且中心部分比栅极导体30短。

公开(公告)号：JP2002289691A

公开(公告)日：2002-10-04

申请号：JP2002021019

申请日：2002-01-30

Applicant: IBM

Inventor： CLEVENGER LAWRENCE A ,  NESBIT LARRY A

IPC: H01L23/522 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532

Abstract: PROBLEM TO BE SOLVED: To provide a structure and method of forming a dual-damascene structure. SOLUTION: The method (and structure) of forming interconnection on a semiconductor substrate includes a step for forming a relatively narrow first structure in a dielectric material formed on the semiconductor substrate, a step for forming a relatively wide second structure in the dielectric material formed on the semiconductor substrate, a step for forming a liner in the first and second structure so that the first structure is substantially filled with the liner and the second structure is not substantially filled, with the liner and a step for metallizing the liner to completely fill the second structure.

公开(公告)号：JPH11330244A

公开(公告)日：1999-11-30

申请号：JP9247299

申请日：1999-03-31

Applicant: SIEMENS AG ,  IBM

Inventor： CLEVENGER LAWRENCE A ,  FILIPPI RONALD G ,  HOINKIS MARK ,  HURD JEFFERY L ,  IGGULDEN ROY C ,  PALM HERBERT ,  POETZLBERGER HANS W ,  RODBELL KENNETH P ,  SCHNABEL FLORIAN ,  WEBER STEFAN ,  MEHTER EBRAHIM A

IPC: H01L21/28 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532

Abstract: PROBLEM TO BE SOLVED: To provide an interconnection with a damascene structure having an improved reliability, by using a liner for surrounding or sealing a conductor to give random crystal grain orientation to a conductive material. SOLUTION: A layer 137 is deposited on an insulating layer 130. A layer for lining the wall and the bottom of the contact opening functions as a base coat or liner for a conductive layer 138 to be subsequently deposited to fill the contact opening, and the degree of crystal grain orientation randomness of a material that fills the damascene structure is expanded. A parameter used for depositing a TiN layer is selected to expand the degree of base coat crystal grain orientation randomness and/or amorphous characteristics. The liner has an enough thickness to ensure the random crystal grain orientation of the conductive material to be subsequently deposited. Thus, the interconnection in an IC having the improved reliability can be obtained.

公开(公告)号：MY120870A

公开(公告)日：2005-11-30

申请号：MYPI20011041

申请日：2001-03-07

Applicant: IBM

Inventor： NAEEM MUNIR D ,  CLEVENGER LAWRENCE A

IPC: H01L21/28 ,  H01L21/768

Abstract: A METHOD OF FORMING NANO-SCALE FEATURES WITH CONVENTIONAL MULTILAYER STRUCTURE, AND NANO-SCALE FEATURES FORMED THEREBY. THE METHOD GENERALLY ENTAILS FORMING A MULTILAYER STRUCTURE THAT INCLUDES A POLYCRYSTALLINE LAYER AND AT LEAST ONE CONSTRAINING LAYER. THE MULTILAYER STRUCTURE IS PATTERNED TO FORM FIRST AND SECOND STRUCTURES, EACH OF WHICH INCLUDES THE POLYCRYSTALLINE AND CONSTRAINING LAYERS. AT LEAST THE FIRST STRUCTURE IS THEN LOCALLY HEATED, DURING WHICH TIME THE CONSTRAINING LAYER RESTRICTS THE THERMAL EXPANSION OF THE POLYCRYSTALLINE LAYER OF THE FIRST STRUCTURE. AS A RESULT, STRESSES ARE INDUCED IN THE POLYCRYSTALLINE LAYER OF THE FIRST STRUCTURE. AS A RESULT, STRESSES ARE INDUCED IN THE POLYCRYSTALLINE LAYER OF THE FIRST STRUCTURE, CAUSING SUBSTANTIALLY TWO-DIMENSIONAL GRAIN GROWTH FROM THE EDGE OF THE FIRST STRUCTURE. SUFFICIENT GRAIN GROWTH OCCURS TO PRODUCE A THIRD STRUCTURE WHICH, BASED ON THE GRAIN SIZE OF THE POLYCRYSTALLINE LAYER, WILL BE A NANO-SCALE STRUCTURE. WHEN APPROPRIATELY CONFIGURED, NANO-SCALE STRUCTURES CAN BE FORMED AS OPERATIVE COMPONENTS OF ELECTRICAL, MENCHANICAL, OPTICAL AND FLUID-HANDLING DEVICES.

公开(公告)号：CA2118147A1

公开(公告)日：1995-04-30

申请号：CA2118147

申请日：1994-10-14

Applicant: IBM

Inventor： CABRAL CYRIL JR ,  CLEVENGER LAWRENCE A ,  D HEURLE FRANCOIS M ,  HARPER JAMES M E ,  MANN RANDY W ,  MILES GLEN L ,  RAKOWSKI DONALD W D

IPC: C23C20/02 ,  C30B1/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  C30B31/02

Abstract: The phase transformation temperature of a metal silicide layer formed overlying a silicon layer on a semiconductor wafer is lowered. First, a refractory metal is disposed proximate to the surface of the silicon layer, a precursory metal is deposited in a layer overlying the refractory metal, and the wafer is heated to a temperature sufficient to form the metal silicide from the precursory metal. The precursory metal may be a refractory metal, and is preferably titanium, tungsten, or cobalt. The concentration of the refractory metal at the surface of the silicon layer is preferably less than about 10 atoms/cm . The refractory metal may be Mo, Co, W, Ta, Nb, Ru, or Cr, and more preferably is Mo or Co. The heating step used to form the silicide is performed at a temperature less than about 700 DEG C, and more preferably between about 600-700 DEG C. Optionally, the wafer is annealed following the step of disposing the refractory metal and prior to the step of depositing the precursory metal layer. Preferably, this annealing step is performed at a wafer temperature of at least about 900 DEG C.