公开(公告)号：JPH1154454A

公开(公告)日：1999-02-26

申请号：JP19988497

申请日：1997-07-25

Applicant: IBM

Inventor： CABRAL JR CYRIL ,  LAWRENCE ALFRED CLEVENGER ,  FRANCOIS MAXDOLE ,  HARPER JAMES M E ,  MANN RANDY W ,  GLENN LESTER MILES ,  NAKOS JAMES S ,  RONEN ANDREW ROY ,  CATHERINE L SAENGER

IPC: C22C14/00 ,  C30B3/00 ,  H01L21/28

Abstract: PROBLEM TO BE SOLVED: To provide an improved method for forming a C54 phase titanium silicide without requiring a second high-temperature annealing. SOLUTION: A low resistivity titanium silicide and semiconductor devices incorporating the same are formed by a titanium alloy comprising titanium and 1-20 atom percent refractory metal deposited in a layer overlying a silicon substrate. The substrate is then heated to a temperature which is sufficient to practically form a C54 phase titanium silicide. The titanium alloy may further comprise silicon and the refractory metal may be Mo, W, Ta, Nb, V, or Cr, but more preferably be Ta or Nb. The heating step used to form the low resistivity titanium silicide is performed at a temperature less than 900 deg.C, and more preferably between about 600 to 700 deg.C.

公开(公告)号：JP2004080036A

公开(公告)日：2004-03-11

申请号：JP2003292574

申请日：2003-08-12

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CLEVENGER LAWRENCE A ,  FENG GEORGE C ,  HARPER JAMES M E ,  LEWIS L SUU

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/4991 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/6659

Abstract: PROBLEM TO BE SOLVED: To provide a method for improving performance in a microelectronic circuit. SOLUTION: A method and a structure for an integrated circuit transistor include a gate conductor having a first conductive material and a second material. The structure has a spacer that is adjacent to the gate conductor and cannot be deformed, and the gap between the gate conductor and the spacer. The first conductive material can be polysilicon, and the second material can be either metal or a polymer. The second material operates as a place holder for the gap. An environmental gas is contained by the gap, and resistance in the gate conductor is reduced. COPYRIGHT: (C)2004,JPO

公开(公告)号：CA1156603A

公开(公告)日：1983-11-08

申请号：CA388982

申请日：1981-10-29

Applicant: IBM

Inventor： CUOMO JEROME J ,  HARPER JAMES M E

IPC: C23F4/00 ,  C23C14/48 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/31 ,  H01L21/316 ,  H01L39/24 ,  H01L49/00 ,  C23C15/00

Abstract: YO980-051 LOW ENERGY ION BEAM OXIDATION PROCESS A surface reaction process for controlled oxide growth is disclosed using a directed, low energy ion beam for compound or oxide formation. The technique is evaluated by fabricating Ni-oxide-Ni and Cr-oxide-Ni tunneling junctions, using directed oxygen ion beams with energies ranging from about 30 to 180 eV. In one embodiment, high ion current densities are achieved at these low energies by replacing the conventional dual grid extraction system of the ion source with a single fine mesh grid. Junction resistance decreases with increasing ion energy, and oxidation time dependence shows a characteristic saturation, both consistent with a process of simultaneous oxidation and sputter etching, as in the conventional r.f. oxidation process. In contrast with r.f. oxidized junctions, however, ion beam oxidized junctions contain less contamination by backsputtering, and the quantitative nature of ion beam techniques allows greater control over the growth process.

公开(公告)号：CA2118147A1

公开(公告)日：1995-04-30

申请号：CA2118147

申请日：1994-10-14

Applicant: IBM

Inventor： CABRAL CYRIL JR ,  CLEVENGER LAWRENCE A ,  D HEURLE FRANCOIS M ,  HARPER JAMES M E ,  MANN RANDY W ,  MILES GLEN L ,  RAKOWSKI DONALD W D

IPC: C23C20/02 ,  C30B1/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  C30B31/02

Abstract: The phase transformation temperature of a metal silicide layer formed overlying a silicon layer on a semiconductor wafer is lowered. First, a refractory metal is disposed proximate to the surface of the silicon layer, a precursory metal is deposited in a layer overlying the refractory metal, and the wafer is heated to a temperature sufficient to form the metal silicide from the precursory metal. The precursory metal may be a refractory metal, and is preferably titanium, tungsten, or cobalt. The concentration of the refractory metal at the surface of the silicon layer is preferably less than about 10 atoms/cm . The refractory metal may be Mo, Co, W, Ta, Nb, Ru, or Cr, and more preferably is Mo or Co. The heating step used to form the silicide is performed at a temperature less than about 700 DEG C, and more preferably between about 600-700 DEG C. Optionally, the wafer is annealed following the step of disposing the refractory metal and prior to the step of depositing the precursory metal layer. Preferably, this annealing step is performed at a wafer temperature of at least about 900 DEG C.

公开(公告)号：SG70654A1

公开(公告)日：2000-02-22

申请号：SG1998003808

申请日：1997-09-23

Applicant: IBM

Inventor： HARPER JAMES M E ,  GEFFKEN ROBERT M

IPC: H05K3/46 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/055 ,  H01L23/525

Abstract: A multilayer interconnected electronic component having increased electromigration lifetime is provided. The interconnections are in the form of studs and comprise vertical side walls having a refractory metal diffusion barrier liner along the sidewalls. The stud does not have a barrier layer at the base thereof and the base of the stud contacts the metallization on the dielectric layer of the component. An adhesion layer can be provided between the base of the stud and the surface of the metallization and the adhesion layer may be continuous or discontinuous. The adhesion layer is preferably a metal such as aluminum which dissolves in the stud or metallization upon heating of the component during fabrication or otherwise during use of the component. A preferred component utilizes a dual Damascene structure.