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    Image sensor and method of manufacturing the same
    22.
    发明专利
    Image sensor and method of manufacturing the same 有权
    图像传感器及其制造方法

    公开(公告)号：JP2011054963A

    公开(公告)日：2011-03-17

    申请号：JP2010186851

    申请日：2010-08-24

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： GAMBINO JEFFREY P ,  ELLIS-MONAGHAN JOHN JOSEPH ,  ADKISSON JAMES WILLIAM ,  LEIDY ROBERT KENNETH

    IPC: H01L27/14 ,  H01L27/146

    CPC classification number: H01L27/14643 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/1464 ,  H01L27/14683 ,  H01L27/14685

    Abstract: PROBLEM TO BE SOLVED: To provide a solid-state image sensor and a method of manufacturing the same. SOLUTION: A solid-state image sensor has a substrate on which a photosensitive region is provided. In the solid-state image sensor, an nonuniform reflection layer is arranged, on a side opposite to the incidence side of the emitted light of the photosensitive region. The nonuniform reflecting layer has a shape for reflecting an incident emitted light that is not captured by one photosensitive region at first to return it to the photosensitive area, whereas which does not reflect the incident emitted light that is not captured by the one photosensitive region, at first, to other photosensitive region provided adjacent to the one photosensitive region on the substrate. COPYRIGHT: (C)2011,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种固态图像传感器及其制造方法。 解决方案：固态图像传感器具有设置有感光区域的基板。 在固态图像传感器中，在与感光区域的发射光的入射侧相反的一侧上布置不均匀的反射层。 不均匀反射层具有用于反射未被一个感光区域捕获的入射发射光首先返回到感光区域的形状，而不反射未被一个感光区域捕获的入射发射光， 首先是与衬底上的一个感光区域相邻设置的其它感光区域。 版权所有（C）2011，JPO＆INPIT

    Method of reducing stress within metallic cover of integrated circuit, and integrated circuit produced using the method
    25.
    发明专利
    Method of reducing stress within metallic cover of integrated circuit, and integrated circuit produced using the method 审中-公开
    集成电路金属外壳中应力减小的方法和使用该方法生产的集成电路

    公开(公告)号：JPH11274158A

    公开(公告)日：1999-10-08

    申请号：JP4899

    申请日：1999-01-04

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレイション

    Inventor： ARNDT KENNETH C ,  CONTI RICHARD A ,  DOBUZINSKY DAVID M ,  ECONOMIKOS LAERTIS ,  GAMBINO JEFFREY P ,  HOH PETER D ,  NARAYAN CHANDRASEKHAR

    IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768

    CPC classification number: H01L21/76804 ,  H01L21/32136 ,  H01L21/76835 ,  H01L21/76885

    Abstract: PROBLEM TO BE SOLVED: To check cracks within a final passivation laver 13 of an integrated circuit by reducing the stresses within a peripheral dielectric which are due to acute corner of a circuit pattern.
    SOLUTION: Stresses generally induced inside a dielectric is reduced by formings 15 and 17, at lower corner 14" of a circuit pattern 11 before adhering an outer layer (that is, a passivation layer) 13. When patterning it by metallic RIE process, this kind of rounding of the corner is achieved by a two-step metallic etching process, including the first step of creating a vertical sidewall and the second step of tapering the lower part of the vertical sidewall or creating a tapered spacer 15 along the under section of the vertical sidewall. When patterning it by a die machine process, this kind of rounding of the corner is achieved by a two-step trench etching process, including a first step of creating a vertical sidewall and a second step of creating a tapered side wall along the under section of the vertical sidewall.
    COPYRIGHT: (C)1999,JPO

    Abstract translation: 要解决的问题：通过减少外围电介质中由于电路图案的急剧拐角引起的应力来检查集成电路的最终钝化层13内的裂纹。 解决方案：在粘附外层（即钝化层）13之前的电路图案11的下角14“处，通过结构15和17减小电介质内部的应力。当通过金属RIE工艺对其进行图案化时， 通过两步金属蚀刻工艺实现角部的圆角化，包括形成垂直侧壁的第一步骤和使垂直侧壁的下部逐渐变细的第二步骤或者沿着垂直侧壁的下部形成锥形间隔件15 垂直侧壁，当通过模具机加工对其进行图案化时，通过两步沟槽蚀刻工艺实现角部圆化，包括形成垂直侧壁的第一步骤和产生锥形侧壁的第二步骤 沿着垂直侧壁的下部。

    POLISHING PROCESS FOR POLYCRYSTALLINE SILICON AND SLURRY SUITABLE FOR THE SAME
    26.
    发明专利
    POLISHING PROCESS FOR POLYCRYSTALLINE SILICON AND SLURRY SUITABLE FOR THE SAME 失效

    公开(公告)号：JPH11265862A

    公开(公告)日：1999-09-28

    申请号：JP533099

    申请日：1999-01-12

    Applicant: IBM

    Inventor： GAMBINO JEFFREY P ,  JASO MARK A

    IPC: B24B37/00 ,  H01L21/304 ,  H01L21/321

    Abstract: PROBLEM TO BE SOLVED: To provide a process which is capable of minimizing the corrosion of an insulator at the edge section of an array, during the selective chemical mechanical polishing(CMP) of a silicon wafer. SOLUTION: A polishing process which can reduce the corrosion of a polishing stopping layer 4 includes the use of a slurry composed of particles and an alkali solution. The slurry which reduces the corrosion of the layer 4 is prepared by mixing solid particles having fine particle sizes in the alkali solution at a mixing ratio of about 0.2 wt.% to about 0.4 wt.% and furthermore increasing the chemical component of the alkali solution. The pH of the slurry is adjusted to be between about 9.5 and about 10.5.

    LOW-TEMP. BPSG DEPOSITION METHOD, BPSG FILM AND INTEGRATED CIRCUIT FORMED BY THE SAME METHOD
    27.
    发明专利
    LOW-TEMP. BPSG DEPOSITION METHOD, BPSG FILM AND INTEGRATED CIRCUIT FORMED BY THE SAME METHOD 失效

    公开(公告)号：JPH1050700A

    公开(公告)日：1998-02-20

    申请号：JP13459897

    申请日：1997-05-26

    Applicant: IBM

    Inventor： AJMERA ATUL C ,  GAMBINO JEFFREY P ,  NGUYEN SON VAN

    IPC: H01L21/768 ,  C23C16/40 ,  H01L21/3105 ,  H01L21/316 ,  H01L23/522

    Abstract: PROBLEM TO BE SOLVED: To improve the pore-filling characteristic by depositing a doped thin boron phosphide silicate glass film on a semiconductor substrate and annealing this film to finally deposit a thin phase boron phosphide silicate glass film. SOLUTION: A gate oxide layer 12 is deposited on a substrate, a polysilicon- silicon oxide layer 14 and Si layer 16 are formed on the layer 12, a thin film layer 20 is formed on the surfaces of the layers 14, 16, and a boron phosphide silicate glass layer 22 is deposited on this layer 20 and annealed, finally form a thin phase boron phosphide silicate glass layer 22. Thus it is possible to provide a good pore-filling characteristic and hold a capability of gettering such moving ions.

    Ferro-electric capacitor modules, methods of manufacture and design structures
    28.
    发明专利
    Ferro-electric capacitor modules, methods of manufacture and design structures 未知

    公开(公告)号：GB2494362B

    公开(公告)日：2015-05-20

    申请号：GB201300268

    申请日：2011-06-23

    Applicant: IBM

    Inventor： GAMBINO JEFFREY P ,  MOON MATTHEW D ,  MURPHY WILLIAM J ,  NAKOS JAMES S ,  PASTEL PAUL W ,  PHILIPS BRETT A

    IPC: H01L27/115 ,  H01L21/28 ,  H01L29/78

    Abstract: Ferro-electric capacitor modules, methods of manufacture and design structures. The method of manufacturing the ferro-electric capacitor includes forming a barrier layer on an insulator layer of a CMOS structure. The method further includes forming a top plate and a bottom plate over the barrier layer. The method further includes forming a ferro-electric material between the top plate and the bottom plate. The method further includes encapsulating the barrier layer, top plate, bottom plate and ferro-electric material with an encapsulating material. The method further includes forming contacts to the top plate and bottom plate, through the encapsulating material. At least the contact to the top plate and a contact to a diffusion of the CMOS structure are in electrical connection through a common wire.

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