公开(公告)号：JP2006286002A

公开(公告)日：2006-10-19

申请号：JP2006102826

申请日：2006-04-04

Applicant: Internatl Business Mach Corp ,  Sony Computer Entertainment Inc ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation ,  株式会社ソニー・コンピュータエンタテインメント

Inventor： YAMAZAKI TAKESHI ,  BROWN JEFFREY D ,  CLARK SCOTT D ,  JOHNS CHARLES RAY

IPC: G06F15/17 ,  G06F12/06 ,  G06F12/08

CPC classification number: G06F12/0831 ,  G06F12/0813 ,  G06F2212/251 ,  G06F2212/253

Abstract: PROBLEM TO BE SOLVED: To perform data consistency management required in some conditions for sharing data. SOLUTION: By means of this method/device, the following steps are provided steps for: transmitting a data command from one device among a plurality of devices to a second address concentration part AC1B inside one processor system 100B among a plurality of processor systems 100; selecting one processor system 100A, which is another processor system storing data transmitted by the data command in itself; transmitting the data command to a first address concentration part AC0A of the selected processor system 100A; and broadcasting the data command from the first address concentration part AC0A of the selected processor system 100A to the second address concentration part AC1 included in each of a plurality of processor systems 100. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：在某些条件下执行数据一致性管理以共享数据。 解决方案：通过该方法/设备，提供以下步骤：将多个设备中的一个设备的数据命令从多个处理器中的一个处理器系统100B内的第二地址集中部分AC1B发送到多个处理器 系统100; 选择一个处理器系统100A，其是存储由数据命令本身发送的数据的另一个处理器系统; 将所述数据命令发送到所选择的处理器系统100A的第一地址集中部分AC0A; 并将数据命令从所选择的处理器系统100A的第一地址集中部分AC0A广播到包括在多个处理器系统100中的每个处理器系统100中的第二地址浓度部分AC1。（C）2007，JPO＆INPIT

公开(公告)号：JP2006133228A

公开(公告)日：2006-05-25

申请号：JP2005320851

申请日：2005-11-04

Applicant: Internatl Business Mach Corp ,  Sony Computer Entertainment Inc ,  Toshiba Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation ,  株式会社ソニー・コンピュータエンタテインメント ,  株式会社東芝

Inventor： GORDON MELIA F ,  JOHNS CHARLES RAY ,  KIHARA HIROKI ,  TAKIGUCHI ITSUKI ,  TAMURA TETSUJI ,  WANG MICHAEL FAN ,  YAZAWA KAZUAKI ,  YOSHIDA MUNEHIRO

IPC: G01K7/00 ,  G01R31/26 ,  H01L21/822 ,  H01L27/04

CPC classification number: G01K15/00 ,  G01R31/2856 ,  G01R31/2874 ,  G01R31/31704 ,  G01R31/319 ,  G01R31/31908

Abstract: PROBLEM TO BE SOLVED: To efficiently calibrate a temperature detection circuit provided on an integrated circuit die.
SOLUTION: The integrated circuit die includes a memory 204 and the temperature detection circuit 200. The memory 204 stores calibration data. The temperature detection circuit 200 is operatively coupled to the memory 204, and receives an input signal. The temperature detection circuit is configured to produce an output signal dependent upon the input signal and indicative of whether a temperature of the integrated circuit die is greater than a selected temperature. During a normal operating mode, the input signal comprises the calibration data.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：有效地校准设置在集成电路管芯上的温度检测电路。 集成电路管芯包括存储器204和温度检测电路200.存储器204存储校准数据。 温度检测电路200可操作地耦合到存储器204，并接收输入信号。 温度检测电路被配置为根据输入信号产生输出信号，并且指示集成电路管芯的温度是否大于所选择的温度。 在正常操作模式期间，输入信号包括校准数据。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JPH1074263A

公开(公告)日：1998-03-17

申请号：JP8675497

申请日：1997-04-04

Applicant: IBM

Inventor： BUI THUY-LINH TRAN ,  JOHNS CHARLES RAY ,  ROBERSON JOHN THOMAS ,  SPANNAUS JOHN FRED

IPC: G06F5/00 ,  G06F3/14 ,  G06T11/00 ,  G06T15/00

Abstract: PROBLEM TO BE SOLVED: To effectively distribute a graphic function between a host computer and a graphic subsystem. SOLUTION: A depth, an alpha, a stencil, and other pixel data are stored in a system memory including one or plural auxiliary graphic buffers. A main processor 11 in a host system generates pixel data related to an image. Whether the data are to be stored in the auxiliary buffer or not is inspected. A mask is generated from a host system in accordance with a result of an inspection. In the case of a spun width and a color interpolation, a color base, color increment data and the X and Y addresses of a 1st pixel are combined as a mask and a mask is transferred to a graphics subsystem by a burst mode. In a subsystem, a mask is used together with other data in order to load a part of the pixel data regulated by a mask to a frame buffer.

公开(公告)号：WO2006095838B1

公开(公告)日：2007-03-15

申请号：PCT/JP2006304659

申请日：2006-03-02

Applicant: SONY COMPUTER ENTERTAINMENT INC ,  IBM

Inventor： CLARK SCOTT DOUGLAS ,  JOHNS CHARLES RAY ,  KROLAK DAVID JOHN ,  YAMAZAKI TAKESHI ,  BROWN JEFFREY DOUGLAS

IPC: G06F13/362

CPC classification number: G06F13/362 ,  G06F1/3237 ,  G06F1/3253 ,  Y02D10/128 ,  Y02D10/151

Abstract: A data switch, a method and a computer program are provided for the transfer of data between multiple bus units in a memory system. Each bus unit is connected to a corresponding data ramp. Each data ramp is only directly connected to the adjacent data ramps. This forms at least one data ring that enables the transfer of data from each bus unit to any other bus unit in the memory system. A central arbiter manages the transfer of data between the data ramps and the transfer of data between the data ramp and its corresponding bus unit. A preferred embodiment contains four data rings, wherein two data rings transfer data clockwise and two data rings transfer data counter-clockwise.

Abstract translation: 提供数据开关，方法和计算机程序用于在存储器系统中的多个总线单元之间传送数据。 每个总线单元连接到相应的数据斜坡。 每个数据斜坡仅直接连接到相邻的数据斜坡。 这形成至少一个数据环，其使得能够将数据从每个总线单元传送到存储器系统中的任何其它总线单元。 中央仲裁器管理数据斜坡之间的数据传输和数据斜坡与其相应总线单元之间的数据传输。 优选实施例包含四个数据环，其中两个数据环顺时针传送数据，两个数据环逆时针传送数据。

公开(公告)号：WO2006006084A3

公开(公告)日：2006-07-20

申请号：PCT/IB2005003169

申请日：2005-07-06

Applicant: SONY COMPUTER ENTERTAINMENT INC ,  IBM

Inventor： DAY MICHAEL NORMAN ,  JOHNS CHARLES RAY ,  LIU PEICHUN PETER ,  TRUONG THUONG QUANG ,  YAMAZAKI TAKESHI

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: A method, an apparatus, and a computer program are provided for controlling memory access. Direct Memory Access (DMA) units have become commonplace in a number of bus architectures. However, managing limited system resources has become a challenge with multiple DMA units. In order to mange the multitude of commands generated and preserve dependencies, embedded flags in commands or a barrier command are used. These operations then can control the order in which commands are executed so as to preserve dependencies.

Abstract translation: 提供了一种用于控制存储器访问的方法，装置和计算机程序。 直接存储器访问（DMA）单元在许多总线体系结构中已经司空见惯。 但是，管理有限的系统资源已成为多个DMA单元的挑战。 为了管理生成的大量命令并保留依赖关系，可以使用命令中的嵌入标志或屏障命令。 这些操作可以控制执行命令的顺序，从而保持依赖关系。

公开(公告)号：CA2505610C

公开(公告)日：2009-06-23

申请号：CA2505610

申请日：2003-11-21

Applicant: IBM

Inventor： DAY MICHAEL NORMAN ,  HOFSTEE HARM PETER ,  TRUONG THUONG QUANG ,  KAHLE JAMES ALLAN ,  JOHNS CHARLES RAY ,  SHIPPY DAVID

IPC: G06F12/10 ,  G06F12/12

Abstract: Memory management in a computer system is improved by preventing a subset of address translation information from being replaced with other types of address translation information in a cache memory reserved for storing such address translation information for faster access by a CPU. This way, the CP U can identify the subset of address translation information stored in the cac he.

公开(公告)号：DE602005008747D1

公开(公告)日：2008-09-18

申请号：DE602005008747

申请日：2005-07-18

Applicant: SONY COMPUTER ENTERTAINMENT INC ,  IBM

Inventor： DAY MICHAEL NORMAN ,  JOHNS CHARLES RAY ,  LIU PEICHUN PETER ,  TRUONG THUONG ,  YAMAZAKI TAKESHI

IPC: G06F13/28 ,  G06F9/46

Abstract: The present invention provides a method and apparatus for creating memory barriers in a Direct Memory Access (DMA) device. A memory barrier command is received and a memory command is received. The memory command is executed based on the memory barrier command. A bus operation is initiated based on the memory barrier command. A bus operation acknowledgment is received based on the bus operation. The memory barrier command is executed based on the bus operation acknowledgment. In a particular aspect, memory barrier commands are direct memory access sync (dmasync) and direct memory access enforce in-order execution of input/output (dmaeieio) commands.

公开(公告)号：GB2356114B

公开(公告)日：2003-09-10

申请号：GB0015421

申请日：2000-06-26

Applicant: IBM

Inventor： CHELSTOWSKI ILIESE CLAIRE ,  JOHNS CHARLES RAY ,  MINOR BARRY ,  WHITE JNR GEORGE LEOPOLD

IPC: G06T7/20 ,  G06T13/20 ,  G09G5/38 ,  G06T15/00

公开(公告)号：CA2667422C

公开(公告)日：2016-03-29

申请号：CA2667422

申请日：2007-12-19

Applicant: IBM

Inventor： BERRY ROBERT WALTER JR ,  JOHNS CHARLES RAY ,  KURUTS CHRISTOPHER

IPC: G06F1/32

Abstract: A power system couples to a multi-core processor to provide power to the processor. The power system throttles at least one of the cores of the processor when the power that the processor consumes from thepower systemexceeds a predetermined threshold power. The power systemmay reduce the rate of instruction issue by a particular core or clock gate a particular core to provide power throttling. The power system dynamically responds to variance of the actualoutput voltage that processor circuitryreceives from the power system in comparison to an expected output voltage over time and corrects for such variance.

公开(公告)号：DE602005009494D1

公开(公告)日：2008-10-16

申请号：DE602005009494

申请日：2005-07-06

Applicant: SONY COMPUTER ENTERTAINMENT INC ,  IBM

Inventor： DAY MICHAEL NORMAN ,  JOHNS CHARLES RAY ,  LIU PEICHUN PETER ,  TRUONG THUONG QUANG ,  YAMAZAKI TAKESHI

IPC: G06F13/28

Abstract: A method, an apparatus, and a computer program are provided for controlling memory access. Direct Memory Access (DMA) units have become commonplace in a number of bus architectures. However, managing limited system resources has become a challenge with multiple DMA units. In order to mange the multitude of commands generated and preserve dependencies, embedded flags in commands or a barrier command are used. These operations then can control the order in which commands are executed so as to preserve dependencies.