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    System, method, and product for managing data transfers in a network
    22.
    发明专利
    System, method, and product for managing data transfers in a network 未知

    公开(公告)号：AU2003214470A8

    公开(公告)日：2003-11-10

    申请号：AU2003214470

    申请日：2003-04-01

    Applicant: IBM

    Inventor： BEUKEMA BRUCE LEROY ,  NEAL DANNY MARVIN ,  RECIO RENATO JOHN ,  GREGG THOMAS ANTHONY

    IPC: G06F9/54 ,  H04L12/28 ,  H04L12/56 ,  H04L29/06 ,  H04L29/08 ,  G06F13/42 ,  G06F15/17 ,  G06F13/12 ,  G06F13/40

    Abstract: A method, system, and product in a data processing system are disclosed for managing data transmitted from a first end node to a second end node included in the data processing system. A logical connection is established between the first end node and the second end node prior to transmitting data between the end nodes. An instance number is associated with this particular logical connection. The instance number is included in each packet transmitted between the end nodes while this logical connection remains established. The instance number remains constant during this logical connection. The instance number is altered, such as by incrementing it, each time a logical connection between these end nodes is reestablished. Thus, each packet is associated with a particular instance of the logical connection. When a packet is received, the instance number included in the packet may be used to determine whether the packet is a stale packet transmitted during a previous logical connection between these end nodes.

    23.
    发明专利
    未知

    公开(公告)号：BR0003217A

    公开(公告)日：2001-03-13

    申请号：BR0003217

    申请日：2000-07-31

    Applicant: IBM

    Inventor： KELLEY RICHARD ALLEN ,  NEAL DANNY MARVIN ,  THURBER STEVEN MARK

    IPC: G06F13/36 ,  G06F13/362 ,  G06F13/364 ,  G06F13/40 ,  G06F13/366

    Abstract: A bus arbiter for a computer system having a bus for connection to a plurality of bus devices where each bus device requests control of bus by use of a bus request signal. The bus arbiter contains logic which incorporates a fairness scheme for controlling and prioritizing the bus request signals based on a predetermined priority of each bus device and each bus device's prior access within a fairness cycle. Each device's prior access is tracked by bits in a data register and is determined by whether or not the device actually received or sent information over the bus, and not by a simple granting of access which could result in a retry signal.

    28.
    发明专利
    未知

    公开(公告)号：DE69914966D1

    公开(公告)日：2004-04-01

    申请号：DE69914966

    申请日：1999-04-19

    Applicant: IBM

    Inventor： BOSSEN DOUGLAS CRAIG ,  MCLAUGHLIN CHARLES ANDREW ,  NEAL DANNY MARVIN ,  NICHOLSON JAMES OTTO ,  THURBER STEVEN MARK

    IPC: G06F13/00 ,  G06F11/07 ,  G06F11/00

    Abstract: Device selects lines 202n from each I/O device 132 are brought into a PCI host bridge 124 individually so that the device number of a failing device may be logged in an error register 204 when an error is seen on the PCI bus. Until the error register is reset, subsequent load and store operations are delayed until the device number of the subject device may be checked against the error register. If the subject device is a previously failing device, the load/store operation to that device is prevented from completing, either by forcing bad parity or zeroing all byte enables. By forcing bad parity or zero byte enables, the I/O device will respond to the load or store request by activating its device select line, but will not accept store data. Operations to devices which are not logged in the error register are permitted to proceed normally, as are all load store operations when the error register is clear. Normal system operations are thus not impacted, and operations during error recovery are permitted to proceed if no further damage will be caused by such operations.

    A method and apparatus for adding and removing components of a data processing system without powering down
    29.
    发明专利
    A method and apparatus for adding and removing components of a data processing system without powering down 未知

    公开(公告)号：GB2334120B

    公开(公告)日：2001-05-02

    申请号：GB9909356

    申请日：1997-09-30

    Applicant: IBM

    Inventor： GUTHRIE GUY LYNN ,  NEAL DANNY MARVIN ,  KELLEY RICHARD ALLEN

    IPC: G06F13/40 ,  G06F1/00

    Abstract: A method and system for providing the ability to add or remove components of a data processing system without powering the system down ("Hot-plug"). The system includes an arbiter, residing within a Host Bridge, Control & Power logic, and a plurality of in-line switch modules coupled to a bus. Each of the in-line switch modules provide isolation for load(s) connected thereto. The Host Bridge in combination with the Control & Power Logic implement the Hot-plug operations such as ramping up and down of the power to a selected slot, and activating the appropriate in-line switches for communication from/to a load (target/controlling master).

    METHOD AND APPARATUS FOR AN ACCELERATED GRAPHIC PORT USING DIFFERENTIAL SIGNALING
    30.
    发明专利
    METHOD AND APPARATUS FOR AN ACCELERATED GRAPHIC PORT USING DIFFERENTIAL SIGNALING 未知

    公开(公告)号：CA2285878A1

    公开(公告)日：2000-05-12

    申请号：CA2285878

    申请日：1999-10-15

    Applicant: IBM

    Inventor： NEAL DANNY MARVIN ,  KELLEY RICHARD ALLEN ,  CLOUSER PAUL LEE

    IPC: G06F3/14 ,  G09G5/36 ,  G09G5/00

    Abstract: An accelerated graphic port connection is adapted for differential signaling. Two signal lines are provided for each graphic port and chipset connection signal and information is encoded as either a polarity or a magnitude of a voltage difference between the two signal lines. An enhanced graphic chip and chipset includes drivers and receivers capable of handling the differential signaling. The resulting accelerated graphic port architecture supports clocking data on both edges as well as source synchronous clocking. The enhanced accelerated graphic port architecture also supports split transactions, deep read pipelining, and the addition of new bus synchronization commands.

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