公开(公告)号：WO2010008748A8

公开(公告)日：2010-04-22

申请号：PCT/US2009047719

申请日：2009-06-18

Applicant: IBM ,  ANDERSON BRENT A ,  BRYANT ANDRES ,  NOWAK EDWARD J ,  RANKIN JED H

Inventor： ANDERSON BRENT A ,  BRYANT ANDRES ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L21/334

CPC classification number: G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

Abstract: A design structure (100, FIG. 1a) is provided for spacer fill structures (100 and 300) and, more particularly, spacer fill structures (100 and 300), a method of manufacturing and a design structure for reducing device variation is provided. The structure includes a plurality of dummy fill shapes (100) in different areas of a device which are configured such that gate perimeter to gate area ratio will result in a total perimeter density being uniform across a chip.

Abstract translation: 提供了用于间隔物填充结构（100和300）的设计结构（100，图1a），更具体地，提供了间隔件填充结构（100和300），制造方法和用于减小装置变化的设计结构。 该结构包括在器件的不同区域中的多个虚拟填充形状（100），其被配置为使得栅极周边与栅极面积比将导致整个芯片的总周边密度是均匀的。

公开(公告)号：WO2006121903A2

公开(公告)日：2006-11-16

申请号：PCT/US2006017491

申请日：2006-05-05

Applicant: IBM ,  RANKIN JED H ,  WATTS ANDREW J

Inventor： RANKIN JED H ,  WATTS ANDREW J

IPC: G06F17/50

CPC classification number: G03F1/84

Abstract: A photomask (100), method of designing, of fabricating, of designing, a method of inspecting and a system for designing the photomask (100). The photomask (100), includes: a cell region (110), the cell region (110) comprising one or more chip regions (155 A, 155B, 155C, 155D), each chip region (155 A, 155B, 155C, 155D) comprising a pattern of opaque and clear sub-regions corresponding to features of an integrated circuit chip and one or more kerf regions (160A, 160B, 160C, 160D), each kerf region (160A, 160B, 160C, 160D) comprising a pattern of opaque and clear sub-regions corresponding to features of an integrated circuit kerf; a clear region (125A) formed adjacent to a side of a copy region (170A, 170B), the copy region (170A, 170B) comprising opaque and clear sub-regions that are copies of at least a part of the cell region (110); and an opaque region (115) between the clear region (125A, 125B, 125C, 125D) and the cell region (110).

Abstract translation: 光掩模（100），设计方法，设计方法，检测方法以及设计光掩模（100）的系统。 光掩模（100）包括：单元区域（110），单元区域（110）包括一个或多个芯片区域（155A，155B，155C，155D），每个芯片区域（155A，155B，155C，155D ）包括对应于集成电路芯片和一个或多个切口区域（160A，160B，160C，160D）的特征的不透明和透明子区域的图案，每个切口区域（160A，160B，160C，160D）包括图案 对应于集成电路切口的特征的不透明和清晰的子区域; 形成在复制区域（170A，170B）的一侧附近的清晰区域（125A），所述复制区域（170A，170B）包括作为所述单元区域（110A）的至少一部分的复制品的不透明和清晰的子区域 ）; 以及在所述透明区域（125A，125B，125C，125D）和所述单元区域（110）之间的不透明区域（115）。

公开(公告)号：WO2005045900A3

公开(公告)日：2005-11-03

申请号：PCT/US2004037029

申请日：2004-11-05

Applicant: IBM ,  ANDERSON BRENT A ,  NOWAK EDWARD J ,  RANKIN JED H

Inventor： ANDERSON BRENT A ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L21/336 ,  H01L29/786 ,  H01L27/01 ,  H01L21/00 ,  H01L21/8238 ,  H01L21/84

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A FinFET structure and method of forming a FinFET device. The method includes: (a) providing a semiconductor substrate (100), (b) forming a dielectric layer (110) on a top surface (105) of the substrate (100); (c) forming a silicon fin (135) on a top surface (115) of the dielectric layer (110); (d) forming a protective layer (160) on at least one sidewall (150A) of the fin (135); and (e) removing the protective layer (160) from the at least one sidewall (150A) in a channel region (175) of the fin (135). In a second embodiment, the protective layer (160) is converted to a protective spacer (210A).

Abstract translation: FinFET结构和形成FinFET器件的方法。 该方法包括：（a）提供半导体衬底（100），（b）在衬底（100）的顶面（105）上形成介电层（110）; （c）在介电层（110）的顶面（115）上形成硅鳍（135）; （d）在翅片（135）的至少一个侧壁（150A）上形成保护层（160）; 和（e）在翅片（135）的沟道区域（175）中从所述至少一个侧壁（150A）去除保护层（160）。 在第二实施例中，保护层（160）被转换为保护性间隔物（210A）。

公开(公告)号：DE60236375D1

公开(公告)日：2010-06-24

申请号：DE60236375

申请日：2002-12-20

Applicant: IBM

Inventor： RANKIN JED H ,  ABADEER WAGDI W ,  BROWN JEFFREY S ,  CHATTY KIRAN V ,  TONTI WILLIAM R ,  GAUTHIER ROBERT J ,  FRIED DAVID M

IPC: H01L21/82 ,  H01L21/84 ,  H01L23/525 ,  H01L27/06 ,  H01L27/118 ,  H01L27/12

公开(公告)号：AU2002368525A1

公开(公告)日：2004-07-22

申请号：AU2002368525

申请日：2002-12-20

Applicant: IBM

Inventor： ABADEER WAGDI W ,  BROWN JEFFREY S ,  CHATTY KIRAN V ,  TONTI WILLIAM R ,  GAUTHIER ROBERT J JR ,  FRIED DAVID M ,  RANKIN JED H

IPC: H01L21/82 ,  H01L21/84 ,  H01L23/525 ,  H01L27/06 ,  H01L27/118 ,  H01L27/12 ,  H01L21/44

公开(公告)号：GB2487321B

公开(公告)日：2013-12-11

申请号：GB201205682

申请日：2010-10-19

Applicant: IBM

Inventor： ANDERSON BRENT A ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L21/28

Abstract: The present invention relates generally to semiconductor devices and, more specifically, to damascene gates having protected shorting regions and related methods for their manufacture. A first aspect of the invention provides a method of forming a damascene gate with protected shorting regions, the method comprising: forming a damascene gate having: a gate dielectric atop a substrate; a gate conductor atop the gate dielectric; a conductive liner laterally adjacent the gate conductor; a spacer between the conductive liner and the substrate; and a first dielectric atop the gate conductor; removing a portion of the conductive liner; and depositing a second dielectric atop a remaining portion of the conductive liner, such that the second dielectric is laterally adjacent both the first dielectric and the gate.

公开(公告)号：GB2494564A

公开(公告)日：2013-03-13

申请号：GB201221748

申请日：2011-03-23

Applicant: IBM

Inventor： RANKIN JED H ,  JAFFE MARK ,  ANDERSON BRENT A

IPC: G06F3/041 ,  G06F3/042 ,  G06F3/044

Abstract: Disclosed herein are embodiments of an interface device (100, 200) (e.g., a display, touchpad, touchscreen display, etc.) with integrated power collection functions. In one embodiment, a solar cell (110, 210) or solar cell array can be located within a substrate (10) at a first surface (11) and an array (120, 220) of interface elements can also be located within the substrate (10) at the first surface (11) such that portions of the solar cell(s) (110, 210) laterally surround the individual interface elements (121, 221) or groups thereof. In another embodiment, a solar cell (110, 210) or solar cell array (120, 220) can be located within the substrate (10) at a first surface (11) and an array of interface elements (120, 220) can be located within the substrate (10) at a second surface (12) opposite the first surface (11) (i.e., opposite the solar cell or solar cell array). In yet another embodiment, an array of diodes, which can function as either solar cells (110, 210) or sensing elements, can be within a substrate (10) at a first surface (11) and can be wired to allow for selective operation in either a power collection mode or sensing mode.

公开(公告)号：DE112011101076T5

公开(公告)日：2013-01-03

申请号：DE112011101076

申请日：2011-03-23

Applicant: IBM

Inventor： JAFFE MARK D ,  RANKIN JED H ,  ANDERSON BRENT A

IPC: G06F3/042 ,  G06F3/041 ,  G06F3/044

Abstract: Hierin werden Ausführungsformen einer Interface-Einheit (100, 200) (z. B. eines Bildschirms, eines Touchpads, eines berührungsempfindlichen Bildschirms usw.) mit integrierten Stromgewinnungsfunktionen offenbart. In einer weiteren Ausführungsform können eine Solarzelle (110, 210) oder eine Solarzellenmatrix innerhalb eines Substrats (10) an einer ersten Oberfläche (11) angeordnet werden und eine Matrix (120, 220) von Interface-Elementen kann ebenfalls innerhalb des Substrats (10) an der der ersten Oberfläche (11) angeordnet werden, sodass Teile der Solarzelle/n (110, 210) die einzelnen Interface-Elemente (121, 221) oder deren Gruppen seitlich umgeben. Gemäß einer weiteren Ausführungsform können eine Solarzelle (110, 210) oder eine Solarzellenmatrix (120, 220) innerhalb des Substrats (10) an einer ersten Oberfläche (11) angeordnet werden und eine Matrix von Interface-Elementen (120, 220) kann innerhalb des Substrats (10) an einer der ersten Oberfläche (11) gegenüber (d. h. der Solarzelle oder der Solarzellenmatrix gegenüber) liegenden zweiten Oberfläche (12) angeordnet werden. Gemäß noch einer weiteren Ausführungsform kann sich eine Matrix von Dioden, die entweder als Solarzellen (110, 210) oder als Sensorelemente fungieren können, innerhalb eines Substrats (10) an einer ersten Oberfläche (11) angeordnet und so verdrahtet sein, dasmodus oder in einem Sensormodus betrieben werden können.

公开(公告)号：AU2002346519A1

公开(公告)日：2003-06-17

申请号：AU2002346519

申请日：2002-11-25

Applicant: IBM

Inventor： RANKIN JED H ,  SCHNEIDER CRAIN E ,  SMYTH JOHN S ,  WATTS ANDREW J

IPC: G03F7/20 ,  H01L21/027 ,  G03C5/00 ,  G01D18/00 ,  G06F17/50 ,  G06F19/00 ,  G21K5/00

公开(公告)号：SG77259A1

公开(公告)日：2000-12-19

申请号：SG1999003558

申请日：1999-07-17

Applicant: IBM

Inventor： ALLEN ARCHIBALD ,  WHITE FRANCIS R ,  RANKIN JED H ,  MANN RANDY W ,  LASKY JEROME B

IPC: H01L21/285 ,  H01L21/28 ,  H01L21/311

Abstract: A buried butted contact and method for its fabrication are provided which includes a substrate having dopants of a first conductivity type and having shallow trench isolation. Dopants of a second conductivity type are located in the bottom of an opening in said substrate. Ohmic contact is provided between the dopants in the substrate and the low diffusivity dopants that is located on a side wall of the opening. The contact is a metal silicide, metal and/or metal alloy.