公开(公告)号：JP2006196894A

公开(公告)日：2006-07-27

申请号：JP2006001619

申请日：2006-01-06

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： COOLBAUGH DOUGLAS D ,  ESHUN EBENEZER E ,  HOOK TERENCE B ,  RASSEL ROBERT M ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K ,  MURPHY WILLIAM J

IPC: H01L23/36 ,  H01L23/373

CPC classification number: H01C7/1013 ,  H01C1/084 ,  H01L2924/0002 ,  Y10T29/49083 ,  Y10T29/49085 ,  Y10T29/49099 ,  Y10T29/49144 ,  Y10T29/49147 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a resistor that has a heat sink with excellent heat conduction. SOLUTION: This heat sink includes a conduction path that has a high-thermal conductivity metal and other thermal conductors. In order that an electrical resistor may not be short-circuited to earth by this thermal resistor, a thin layer with a high-thermal conductivity electric insulator is interposed between the thermal conductor and the resistor's body. Accordingly, since heat is conducted to the heat sink in a direction in which the thermal conductor with high thermal conductivity moves away from the resistor, the resistor can pass a large amount of current. In addition to the fact that a parasitic capacitance and other electric parasitic actions that help reduce high-frequency responses from the electric resistor are lowered, various structures of a thermal conductor and heat sink are achieved through which favorable thermal conduction characteristics are obtained. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供具有散热器的具有优异热传导性的电阻器。 解决方案：该散热器包括具有高导热性金属和其他热导体的导电路径。 为了使该电阻器不会被该热电阻器短路到地，具有高导热电绝缘体的薄层插入在热导体和电阻体之间。 因此，由于在热导率高的导体从电阻器移开的方向向散热器传导热量，所以电阻器能够通过大量的电流。 除了有助于降低来自电阻器的高频响应的寄生电容和其他电寄生作用降低之外，还实现了热导体和散热器的各种结构，从而获得了良好的热传导特性。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2001313373A

公开(公告)日：2001-11-09

申请号：JP2001098235

申请日：2001-03-30

Applicant: IBM

Inventor： KERRY BERNSTEIN ,  GEFFKEN ROBERT M ,  STAMPER ANTHONY K ,  STEVEN A SAINT ONGE

IPC: H01L23/52 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To provide a metal capacitor installed on a chip. SOLUTION: Capacitors (60, 126) manufactured on a semiconductor chip have strap/contacts (41A, 119A), which mutually connect bottom plates (41B, 111A) of a capacitor to a chip circuit. In one version, an extension part of a material, constituting a bottom plate of a capacitor forms a strap contact. In the other version, a capacitor (185) comprises a folded bottom plate, which uses an available space and therefore increases its capacitance, a dielectric layer and a top plate. By means of a plurality of manufacturing methods, manufacturing of these capacitors of various versions can be incorporated in a standard dual or single-damascene manufacturing process, including a copper damascene process.

公开(公告)号：JPH10289949A

公开(公告)日：1998-10-27

申请号：JP9198298

申请日：1998-04-03

Applicant: IBM

Inventor： CRONIN JOHN E ,  HARTSWICK THOMAS J ,  STAMPER ANTHONY K

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: PROBLEM TO BE SOLVED: To facilitate mutual connection between a connecting wire and a mutual connection stud by using a sidewall spacer on the side face of the connecting wire for widening the contact area between the connecting wire and the connection stud. SOLUTION: A semiconductor part 100 has a connection stud 102 connecting the first connecting wire 104 to the second connecting wire 106. The first connecting wire 104 and the second connecting wire 106 and made of a metallic conductor in high conductivity. A substitute conductive path is formed between the first connecting wire 104 and the mutual connection stud 102 by a sidewall spacer 2 added to the first connecting wire 104 before an insulator is bonded. Especially, the side wall 22 comes into contact with a Ti/TiN layer 108 along the outer side thereof. Furthermore, the connection stud 102 is connected to the sidewall spacer 122 which is further connected to the first connecting wire 104. Accordingly, the sidewall spacer 122 is connected to the first connecting wire 104 along the whole sidewall thereof.

公开(公告)号：JP2004228569A

公开(公告)日：2004-08-12

申请号：JP2004003456

申请日：2004-01-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： COONEY III EDWARD C ,  ROBERT M JEFFKEN ,  MCGAHAY VINCENT J ,  MOTSIFF WILLIAM T ,  MURRAY MARK P ,  PIPER AMANDA L ,  STAMPER ANTHONY K ,  THOMAS DAVID C ,  TYBERG CHRISTY S ,  WEBSTER ELIZABETH T

IPC: H01L21/3205 ,  H01L21/768 ,  H01L21/82 ,  H01L23/52 ,  H01L23/522 ,  H01L23/525 ,  H01L23/532

CPC classification number: H01L21/76808 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76892 ,  H01L23/525 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide re-work processing methods of both the level of a single chip connecting or an interconnecting metal and a multilevel. SOLUTION: The method of re-working a BEOL (a back end of a process line) metallization levels of damascene metallurgy comprises the processes of: forming a plurality of BEOL metallization levels 101, 102 on a substrate 110; forming line and via portions in the BEOL metallization level; exposing the line section and the via section by selectively removing at least one BEOL metallization level; and replacing a removed BEOL metallization level with at least one of new BEOL metallization levels. The BEOL metallization levels 101, 102 comprises a first dielectric layers 120, 130 and second dielectric layers 125, 135, and the first dielectric layer includes a material having a dielectric constant lower than that of the second dielectric layer. COPYRIGHT: (C)2004,JPO&NCIPI

Abstract translation: 要解决的问题：提供单芯片连接或互连金属和多层的水平的再加工处理方法。 解决方案：重新加工大马士革冶金的BEOL（工艺线的后端）金属化水平的方法包括以下过程：在衬底110上形成多个BEOL金属化水平101,102; 在BEOL金属化水平上形成线和通孔部分; 通过选择性地去除至少一个BEOL金属化水平来暴露线段和通路部分; 并用至少一个新的BEOL金属化水平替换去除的BEOL金属化水平。 BEOL金属化层101,102包括第一电介质层120,130和第二电介质层125,135，并且第一电介质层包括介电常数低于第二电介质层的介电常数的材料。 版权所有（C）2004，JPO＆NCIPI

公开(公告)号：JP2001313372A

公开(公告)日：2001-11-09

申请号：JP2001090567

申请日：2001-03-27

Applicant: IBM

Inventor： JENNIFER D LYNCH ,  WILBUR D PRISER ,  STAMPER ANTHONY K ,  STEVEN A SAINT ONGE

IPC: H01L21/28 ,  H01L21/283 ,  H01L21/70 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L27/02 ,  H01L27/04 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a highly reliable chip-on-capacitor. SOLUTION: The capacitor (94) in a semiconductor device (20) has a lower copper plate (30) in a damascene/trench (22), barrier layers (56, 180a) disposed above the lower plate, a dielectric layer (60) disposed above the barrier layers and an upper plate (96) above the dielectric layer. Another embodiment of this invention is capacitors (296, 396) in a semiconductor device, which has two lower plates (230, 231, 330, 331) mutually separated, dielectric layers (260, 360) above the lower plate and upper plates (296, 396) above the dielectric layer which covers the lower plate, extends preferably across it. This invention further includes a method for manufacturing the capacitor of such a constitution.

公开(公告)号：JP2001313371A

公开(公告)日：2001-11-09

申请号：JP2001073042

申请日：2001-03-14

Applicant: IBM

Inventor： ROBERT M JEFFKEN ,  STAMPER ANTHONY K

IPC: H01L21/3205 ,  H01L21/02 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To provide a metallic capacitor which is provided inside a metal layer on a semiconductor chip. SOLUTION: A lower plate of a capacitor is provided between an insulation layer and a dielectric layer. An insulation layer is disposed adjacent to a metallization layer, and a dielectric layer separates a lower plate of a capacitor from the upper plate of the capacitor. The shoulder part of a lower plate is adjacent to it and brought into contact with a via filled with copper. Although a via extends upward to a common surface of the upper plate, it is electrically isolated from an upper plate. A via also extends downward toward a metallization layer. This structure is formed by a copper dual-damascene process.

公开(公告)号：JP2001308280A

公开(公告)日：2001-11-02

申请号：JP2001070049

申请日：2001-03-13

Applicant: IBM

Inventor： STEPHEN H BALDEMAN ,  STAMPER ANTHONY K

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/82 ,  H01L21/822 ,  H01L23/522 ,  H01L23/525 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To provide a precision circuit element and a method of forming it. SOLUTION: The circuit element is formed as one part of an integrated circuit assembly. The process of the circuit element provides a nominal value of the circuit element that is near to a desired value. An additional trim circuit element is coupled through a link to the nominal circuit element. The Link is a fusible link or an anti fuse. By fusing and cutting the fusible link selectively or by adding or reducing the trim circuit element by fusing the anti fuse, the nominal value of the circuit element is individuated. In a typical example, a capacitor is used.

公开(公告)号：JP2001223340A

公开(公告)日：2001-08-17

申请号：JP2001014867

申请日：2001-01-23

Applicant: IBM

Inventor： KERRY BERNSTEIN ,  NICHOLAS THEODORE SCHMIDT ,  STAMPER ANTHONY K ,  STEVEN ARTHUR SAINT ONJI ,  STEVEN HOWARD VOLDMAN

IPC: H01G4/40 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/822 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To provide an interconnecting level capacitor structure and a forming method thereof. SOLUTION: The capacitor structure comprises a first insulating layer disposed on an interconnecting level surface of an integrated circuit, first and second conductors which are formed in the first insulating layer and are isolated by a trench delimited by the first insulating layer, a first conductive barrier layer which is disposed on the first and second conductors and connects the first and second conductors, a second insulting layer disposed on the first conductive barrier layer, a second conductive barrier layer disposed on the second insulating layer, and a third conductor which is disposed in the trench and on the second conductive barrier layer. A capacitance is increased by using regions on a top surface, a bottom surface, and a side surface of the capacitor structure. It is possible to obtain an on-cap decoupling capacitor having a larger size without sacrificing a precious silicon space.

公开(公告)号：JP2000200832A

公开(公告)日：2000-07-18

申请号：JP36394999

申请日：1999-12-22

Applicant: IBM

Inventor： PAUL D AGUNERO ,  REENA P BUCKWALTER ,  JOHN HAMEL ,  BARBARA LUTHER ,  STAMPER ANTHONY K

IPC: H01L23/522 ,  H01L21/04 ,  H01L21/28 ,  H01L21/318 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To improve adhesiveness of a deposited inorganic barrier film to a copper surface of a copper interconnection structure by including exposure of a copper layer in an interconnected semiconductor structure to a reducing plasma before the formation of the inorganic barrier film on the copper interconnection structure. SOLUTION: A copper interconnection structure is exposed to a reducing plasma before an inorganic barrier film 24 is deposited. This reducing plasma is a non-oxidizing, i.e., oxygen-atom-free plasma atmosphere. A suitable plasma is selected from H2, N2, NH3, and rare gas, but it is not limited to these. Further, a combination of more than two of these reducing plasmas such as N2 and H2 is intended. N2 and NH3 are very preferable among these reducing plasmas. The adhesiveness of the inorganic barrier layer 24 to copper 20 can be improved by using this reducing plasma exposure process.

公开(公告)号：WO2012177304A3

公开(公告)日：2014-03-13

申请号：PCT/US2012029005

申请日：2012-03-14

Applicant: IBM ,  JAHNES CHRISTOPHER V ,  STAMPER ANTHONY K

Inventor： JAHNES CHRISTOPHER V ,  STAMPER ANTHONY K

IPC: B81B3/00

CPC classification number: H01H59/0009 ,  B81B3/001 ,  B81B7/0006 ,  B81B2201/016 ,  B81B2203/0118 ,  B81B2203/04 ,  B81C1/0015 ,  B81C1/00293 ,  B81C2203/0145 ,  G06F17/5045 ,  G06F17/5068 ,  H01H1/0036 ,  H01H2001/0057 ,  Y10T29/49121

Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are provided. The method of forming a MEMS structure includes forming fixed actuator electrodes (115) and a contact point on a substrate. The method further includes forming a MEMS beam (100) over the fixed actuator electrodes and the contact point. The method further includes forming an array of actuator electrodes (105') in alignment with portions of the fixed actuator electrodes, which are sized and dimensioned to prevent the MEMS beam from collapsing on the fixed actuator electrodes after repeating cycling. The array of actuator electrodes are formed in direct contact with at least one of an underside of the MEMS beam and a surface of the fixed actuator electrodes.

Abstract translation: 提供微机电系统（MEMS）结构，制造方法和设计结构。 形成MEMS结构的方法包括在基板上形成固定的致动器电极（115）和接触点。 该方法还包括在固定的致动器电极和接触点上形成MEMS光束（100）。 该方法还包括形成与固定致动器电极的部分对准的致动器电极阵列（105'），其尺寸和尺寸被设计成防止MEMS梁在重复循环之后塌陷在固定的致动器电极上。 致动器电极的阵列形成为与MEMS光束的下侧和固定的致动器电极的表面中的至少一个直接接触。